FreeCalypso > hg > fc-small-hw

annotate duart28/src/vsrc/target_if.v @ 72:c2a3670c7aca

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd3.pcb: manually add bottom strap to LCD footprint
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Nov 2021 06:11:27 +0000
parents 22aba3a61a4b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /* This module captures our target interfaces. */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 module target_if (GND, UART0_TxD, UART0_RxD, UART0_RTS, UART0_CTS,
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 UART0_DTR, UART0_DSR, UART0_DCD, UART0_RI,
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 UART1_TxD, UART1_RxD);
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 input GND;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 input UART0_TxD, UART0_RTS, UART0_DTR;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 output UART0_RxD, UART0_CTS, UART0_DSR, UART0_DCD, UART0_RI;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 input UART1_TxD;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 output UART1_RxD;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 /* main DUART signal set header */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 header_10pin main_if ( .pin_1(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 .pin_2(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 .pin_3(UART1_RxD),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 .pin_4(UART0_RxD),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 .pin_5(UART1_TxD),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 .pin_6(UART0_TxD),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 .pin_7(UART0_DCD),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 .pin_8(UART0_CTS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 .pin_9(UART0_DTR),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 .pin_10(UART0_RTS)
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 /* auxiliary DSR and RI */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 header_3pin aux_if (.pin_1(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 .pin_2(UART0_DSR),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 .pin_3(UART0_RI)
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 endmodule