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comparison lunalcd2/src/Makefile @ 60:38c713964bb7

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lunalcd2: MCL binding complete
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 19:01:35 +0000
parents d5d14b426faa
children df8f40386c0b
comparison
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59:d5d14b426faa 60:38c713964bb7
1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \ 1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
2 vsrc/current_select.v vsrc/lcd_module.v 2 vsrc/current_select.v vsrc/lcd_module.v
3 NETS= sverp.unet 3 NETS= sverp.unet bound.unet
4 4
5 all: ${NETS} 5 all: ${NETS}
6 6
7 sverp.unet: ${VSRCS} primitives Makefile 7 sverp.unet: ${VSRCS} primitives Makefile
8 ueda-sverp -o $@ ${VSRCS} 8 ueda-sverp -o $@ ${VSRCS}
9 9
10 bound.unet: MCL sverp.unet
11 unet-bind -c sverp.unet $@
12
10 clean: 13 clean:
11 rm -f *.unet *.txt *.csv errs elements.pcb 14 rm -f *.unet *.txt *.csv errs elements.pcb