FreeCalypso > hg > fc-small-hw
comparison duart28/design-spec @ 38:ba83a7cd6451
duart28/design-spec: circuit description should be complete
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 23 Jul 2020 19:49:00 +0000 |
| parents | b2d6d8f756ea |
| children | 45bbb72a8916 |
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| 37:b2d6d8f756ea | 38:ba83a7cd6451 |
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| 229 812500 baud. If we populate the same 1 kOhm resistors, the undesirable current | 229 812500 baud. If we populate the same 1 kOhm resistors, the undesirable current |
| 230 in the partial power-down scenario will be 2.8 mA per pin, which is greater | 230 in the partial power-down scenario will be 2.8 mA per pin, which is greater |
| 231 than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors | 231 than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors |
| 232 the current will be 1.27 mA, and we are hoping that 812500 baud communication | 232 the current will be 1.27 mA, and we are hoping that 812500 baud communication |
| 233 will still work OK. | 233 will still work OK. |
| 234 | |
| 235 2.3. UART inputs to the adapter | |
| 236 | |
| 237 We have a total of 6 inputs: RxD, CTS, DSR, DCD, RI and RxD2. These inputs | |
| 238 need to pass through LVC buffers just like the outputs, but for a different | |
| 239 reason. With inputs there is no need for voltage level translation, but the | |
| 240 need for LVC buffers arises because of partial power-down considerations - the | |
| 241 scenario when the Calypso board is fully up and running and is connected to the | |
| 242 DUART adapter, but there is no USB host connected - see section 1.3. If | |
| 243 Calypso UART outputs are connected directly to FT2232D inputs without any | |
| 244 intermediate buffers, this condition is handled very poorly, with about 5.8 mA | |
| 245 of current flowing per pin, which is certainly not acceptable for a proper | |
| 246 design. | |
| 247 | |
| 248 Insertion of an LVC buffer into each input signal path neatly solves this | |
| 249 problem: these buffers are specifically designed for partial power-down | |
| 250 applications and have very small Ioff leakage current - listed as 0.1 uA | |
| 251 typical or 10 uA maximum in the 74LVC541A datasheet. | |
| 252 | |
| 253 One additional complication is that we also have to add explicit pull-up | |
| 254 resistors (to our local 2.8V rail) on each of our 6 inputs in front of the | |
| 255 buffer IC. Many of our UART inputs may be legitimately left unconnected, and | |
| 256 these unconnected inputs should be sensed by our FT2232D USB UART as high. If | |
| 257 we were connecting to FT2232D inputs directly, the FT2232D chip's internal | |
| 258 pull-ups would take care of this condition, but when we have a 74LVC541A buffer | |
| 259 in front of these FT2232D inputs, this buffer IC's own inputs must not be left | |
| 260 floating. | |
| 261 | |
| 262 2.4. LVC buffer details | |
| 263 | |
| 264 We shall use two LVC buffer ICs of the same type (74LVC541A), one for the 4 | |
| 265 outputs, the other for the 6 inputs. Each 74LVC541A is an octal buffer, thus | |
| 266 some slots in each IC remain unused; all unused slots will have their A inputs | |
| 267 tied to GND. Both nOE1 and nOE2 on each buffer IC are also tied to GND, | |
| 268 resulting in all buffers being always enabled. | |
| 269 | |
| 270 The 74LVC541A buffer for outputs will have its Vcc supply pin fed with 2.8V, as | |
| 271 required in order to produce 2.8V logic levels on outputs from the adapter. | |
| 272 However, the other 74LVC541A buffer for inputs will have its Vcc supply pin fed | |
| 273 with 3.3V, same as FT2232D VCCIOA and VCCIOB. | |
| 274 | |
| 275 When the inputs coming from the connected Calypso target have 2.8V logic levels | |
| 276 and ultimately need to go to FT2232D receivers operating at 3.3V, a sort of | |
| 277 translation will have to happen somewhere, with a CMOS input structure operating | |
| 278 with a 3.3V supply being fed 2.8V inputs. We can make this translation happen | |
| 279 in the FT2232D if we use an intermediate LVC buffer powered at 2.8V or no | |
| 280 intermediate buffer at all, or we can make this translation happen in the LVC | |
| 281 buffer if the latter is powered with the same 3.3V as the FT2232D I/O pins. | |
| 282 The second approach has been chosen because the behaviour of 74LVC541A under | |
| 283 these conditions is much better understood than the behaviour of FT2232D I/O | |
| 284 cells under the same, thanks to much better documentation being available for | |
| 285 74LVC541A than for that part of FT2232D. | |
| 286 | |
| 287 Please note, however, that the pull-up resistors on inputs before input-serving | |
| 288 74LVC541A buffer will be wired to our local 2.8V rail, not to 3.3V, even though | |
| 289 the buffer IC will be powered with 3.3V. This way all interface signals exist | |
| 290 strictly in the 2.8V domain and never get exposed to 3.3V in any form. | |
| 291 | |
| 292 2.5. LDO regulators | |
| 293 | |
| 294 Two LDO regulators will be implemented on our adapter board, both powered from | |
| 295 USB 5V: one producing 3.3V, the other producing 2.8V. Our 3.3V LDO will power | |
| 296 FT2232D VCCIOA & VCCIOB and the input-serving 74LVC541A buffer, whereas the | |
| 297 other 2.8V LDO will power our output-serving 74LVC541A buffer and our input | |
| 298 pull-up resistors. Both LDOs will be of TLV702 family from TI, based on our | |
| 299 recent good experiences with this LDO family in other projects. | |
| 300 | |
| 301 The FT2232D chip's built-in 3.3V LDO won't be used: its 5 mA current limit | |
| 302 seems to be too small, and our current FT2232D adapter boards made by PLDkit | |
| 303 don't use it either, using an external beefier LDO instead. |