FreeCalypso > hg > fc-small-hw
comparison lunalcd2/src/vsrc/current_select.v @ 59:d5d14b426faa
lunalcd2: structural Verilog source captured
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 25 Jun 2021 18:44:11 +0000 |
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58:99328e0ff61a | 59:d5d14b426faa |
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1 module current_select (Vio, SET); | |
2 | |
3 input Vio; | |
4 output SET; | |
5 | |
6 wire sw_1mA, sw_2mA, sw_4mA, sw_8mA; | |
7 | |
8 pkg_DIP_SW_x4 dipsw ( .pin_1(Vio), | |
9 .pin_2(sw_8mA), | |
10 .pin_3(Vio), | |
11 .pin_4(sw_4mA), | |
12 .pin_5(Vio), | |
13 .pin_6(sw_2mA), | |
14 .pin_7(Vio), | |
15 .pin_8(sw_1mA) | |
16 ); | |
17 | |
18 resistor R_1mA (sw_1mA, SET); | |
19 resistor R_2mA (sw_2mA, SET); | |
20 resistor R_4mA (sw_4mA, SET); | |
21 resistor R_8mA (sw_8mA, SET); | |
22 | |
23 endmodule |