FreeCalypso > hg > fc-small-hw
comparison duart28c/src/vsrc/application_block.v @ 46:d80978bd645e
duart28c: started with a copy from duart28
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 29 Jul 2020 07:08:28 +0000 |
parents | |
children | 5bdd24aae51e |
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45:2f8a4e3c48cb | 46:d80978bd645e |
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1 /* | |
2 * This module encapsulates the application function of our board: | |
3 * dual UART with 2.8V outputs. | |
4 */ | |
5 | |
6 module application_block (GND, P_3V3, P_2V8, ADBUS, BDBUS); | |
7 | |
8 input GND, P_3V3, P_2V8; | |
9 | |
10 inout [7:0] ADBUS, BDBUS; | |
11 | |
12 /* 2.8V output wires */ | |
13 | |
14 wire TxD_2V8_before_R, RTS_2V8_before_R, DTR_2V8_before_R, TxD2_2V8_before_R; | |
15 wire TxD_2V8_after_R, RTS_2V8_after_R, DTR_2V8_after_R, TxD2_2V8_after_R; | |
16 | |
17 /* input signal wires */ | |
18 | |
19 wire RxD_in, CTS_in, DSR_in, DCD_in, RI_in, RxD2_in; | |
20 | |
21 /* output buffers */ | |
22 | |
23 buffer_ic_common output_buf_common (.Vcc(P_2V8), | |
24 .GND(GND), | |
25 .nOE1(GND), | |
26 .nOE2(GND) | |
27 ); | |
28 | |
29 capacitor output_buf_bypass_cap (P_2V8, GND); | |
30 | |
31 buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8_before_R)); | |
32 buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8_before_R)); | |
33 buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8_before_R)); | |
34 buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8_before_R)); | |
35 | |
36 buffer_ic_slot unused_output_buf1 (.A(GND), .Y()); | |
37 buffer_ic_slot unused_output_buf2 (.A(GND), .Y()); | |
38 buffer_ic_slot unused_output_buf3 (.A(GND), .Y()); | |
39 buffer_ic_slot unused_output_buf4 (.A(GND), .Y()); | |
40 | |
41 /* output series resistors */ | |
42 | |
43 resistor TxD_series_R (TxD_2V8_before_R, TxD_2V8_after_R); | |
44 resistor RTS_series_R (RTS_2V8_before_R, RTS_2V8_after_R); | |
45 resistor DTR_series_R (DTR_2V8_before_R, DTR_2V8_after_R); | |
46 resistor TxD2_series_R (TxD2_2V8_before_R, TxD2_2V8_after_R); | |
47 | |
48 /* input buffers */ | |
49 | |
50 buffer_ic_common input_buf_common (.Vcc(P_3V3), | |
51 .GND(GND), | |
52 .nOE1(GND), | |
53 .nOE2(GND) | |
54 ); | |
55 | |
56 capacitor input_buf_bypass_cap (P_3V3, GND); | |
57 | |
58 buffer_ic_slot buf_RxD (.A(RxD_in), .Y(ADBUS[1])); | |
59 buffer_ic_slot buf_CTS (.A(CTS_in), .Y(ADBUS[3])); | |
60 buffer_ic_slot buf_DSR (.A(DSR_in), .Y(ADBUS[5])); | |
61 buffer_ic_slot buf_DCD (.A(DCD_in), .Y(ADBUS[6])); | |
62 buffer_ic_slot buf_RI (.A(RI_in), .Y(ADBUS[7])); | |
63 buffer_ic_slot buf_RxD2 (.A(RxD2_in), .Y(BDBUS[1])); | |
64 | |
65 buffer_ic_slot unused_input_buf1 (.A(GND), .Y()); | |
66 buffer_ic_slot unused_input_buf2 (.A(GND), .Y()); | |
67 | |
68 /* input pull-up resistors */ | |
69 | |
70 resistor RxD_pullup (RxD_in, P_2V8); | |
71 resistor CTS_pullup (CTS_in, P_2V8); | |
72 resistor DSR_pullup (DSR_in, P_2V8); | |
73 resistor DCD_pullup (DCD_in, P_2V8); | |
74 resistor RI_pullup (RI_in, P_2V8); | |
75 resistor RxD2_pullup (RxD2_in, P_2V8); | |
76 | |
77 /* target interface headers */ | |
78 | |
79 target_if target_if ( .GND(GND), | |
80 .UART0_TxD(TxD_2V8_after_R), | |
81 .UART0_RxD(RxD_in), | |
82 .UART0_RTS(RTS_2V8_after_R), | |
83 .UART0_CTS(CTS_in), | |
84 .UART0_DTR(DTR_2V8_after_R), | |
85 .UART0_DSR(DSR_in), | |
86 .UART0_DCD(DCD_in), | |
87 .UART0_RI(RI_in), | |
88 .UART1_TxD(TxD2_2V8_after_R), | |
89 .UART1_RxD(RxD2_in) | |
90 ); | |
91 | |
92 endmodule |