--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/schem.v	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,106 @@
+module board ();
+
+wire GND, VBAT, Vio;
+wire [15:0] DB;
+wire RD, WR, RS, CS, RESET;
+wire BL_EN, Vbacklight;
+wire [1:3] LEDK;
+
+/* LCD module connector */
+
+conn_36pin_plus2 fpc (  .pin_1(DB[15]),
+			.pin_2(DB[14]),
+			.pin_3(DB[13]),
+			.pin_4(DB[12]),
+			.pin_5(DB[11]),
+			.pin_6(DB[10]),
+			.pin_7(DB[9]),
+			.pin_8(DB[8]),
+			.pin_9(GND),
+			.pin_10(DB[7]),
+			.pin_11(DB[6]),
+			.pin_12(DB[5]),
+			.pin_13(DB[4]),
+			.pin_14(DB[3]),
+			.pin_15(DB[2]),
+			.pin_16(DB[1]),
+			.pin_17(DB[0]),
+			.pin_18(Vio),	/* IOVCC */
+			.pin_19(Vio),	/* VCI */
+			.pin_20(RD),
+			.pin_21(WR),
+			.pin_22(RS),
+			.pin_23(CS),
+			.pin_24(RESET),
+			.pin_25(GND),	/* IM0 tied low */
+			.pin_26(GND),
+			.pin_27(Vbacklight),	/* LEDA */
+			.pin_28(LEDK[1]),
+			.pin_29(LEDK[2]),
+			.pin_30(LEDK[3]),
+			/* the remaining pins are NC */
+			.pin_31(),
+			.pin_32(),
+			.pin_33(),
+			.pin_34(),
+			.pin_35(),
+			.pin_36(),
+			/* ground the two mounting pads */
+			.pin_37(GND),
+			.pin_38(GND)
+	);
+
+/* bypass cap for LCD module core */
+capacitor LCD_bypass_cap (Vio, GND);
+
+/* main interface connector */
+
+header_26pin main_if (  .pin_1(DB[15]),
+			.pin_2(DB[14]),
+			.pin_3(DB[13]),
+			.pin_4(DB[12]),
+			.pin_5(DB[11]),
+			.pin_6(DB[10]),
+			.pin_7(DB[9]),
+			.pin_8(DB[8]),
+			.pin_9(DB[7]),
+			.pin_10(DB[6]),
+			.pin_11(DB[5]),
+			.pin_12(DB[4]),
+			.pin_13(DB[3]),
+			.pin_14(DB[2]),
+			.pin_15(DB[1]),
+			.pin_16(DB[0]),
+			.pin_17(CS),
+			.pin_18(RD),
+			.pin_19(WR),
+			.pin_20(RS),
+			.pin_21(GND),
+			.pin_22(GND),
+			.pin_23(RESET),
+			.pin_24(Vio),
+			.pin_25(BL_EN),
+			.pin_26(GND)
+	);
+
+/* backlight circuit */
+
+header_2pin VBAT_conn ( .pin_1(VBAT),
+			.pin_2(GND)
+	);
+
+capacitor VBAT_bypass_cap (VBAT, GND);
+
+regulator reg ( .IN(VBAT),
+		.OUT(Vbacklight),
+		.GND(GND),
+		.EN(BL_EN)
+	);
+
+capacitor reg_out_cap (Vbacklight, GND);
+
+resistor R1 (LEDK[1], GND);
+resistor R2 (LEDK[2], GND);
+resistor R3 (LEDK[3], GND);
+
+endmodule