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view duart28/src/vsrc/regulator_with_caps.v @ 23:22aba3a61a4b

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duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
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module regulator_with_caps (GND, IN, OUT);

input GND, IN;
output OUT;

regulator_ic reg (.IN(IN),
		  .OUT(OUT),
		  .GND(GND),
		  .EN(IN)
	);

capacitor input_cap (IN, GND);
capacitor output_cap (OUT, GND);

endmodule