FreeCalypso > hg > fc-small-hw
graph
-
lunalcd3.pcb: add orientation marker to SW1Thu, 18 Nov 2021 07:40:13 +0000, by Mychaela Falconia
-
lunalcd3.pcb: layout changes around top bracketThu, 18 Nov 2021 06:55:23 +0000, by Mychaela Falconia
-
lunalcd3.pcb: extend ground plane for top bracket additionThu, 18 Nov 2021 06:45:36 +0000, by Mychaela Falconia
-
lunalcd3.pcb: add top bracket to LCD footprintThu, 18 Nov 2021 06:44:24 +0000, by Mychaela Falconia
-
lunalcd3.pcb: reroute LCD power trace around right ear of bottom bracketThu, 18 Nov 2021 06:29:01 +0000, by Mychaela Falconia
-
lunalcd3.pcb: manually add bottom strap to LCD footprintThu, 18 Nov 2021 06:11:27 +0000, by Mychaela Falconia
-
lunalcd3 project startedThu, 18 Nov 2021 04:59:47 +0000, by Mychaela Falconia
-
lunalcd2/src/Makefile: generate BOM outputsSat, 26 Jun 2021 21:16:48 +0000, by Mychaela Falconia
-
lunalcd2/src/MCL: resistor parts nailed downSat, 26 Jun 2021 21:16:08 +0000, by Mychaela Falconia
-
lunalcd2/src/MCL: different part for two-post VBAT supply headerSat, 26 Jun 2021 20:40:29 +0000, by Mychaela Falconia
-
lunalcd2/pcb: add MakefileFri, 25 Jun 2021 23:08:00 +0000, by Mychaela Falconia
-
lunalcd2.pcb: manual DRC fixesFri, 25 Jun 2021 22:59:37 +0000, by Mychaela Falconia
-
lunalcd2.pcb complete except for DRCFri, 25 Jun 2021 22:52:20 +0000, by Mychaela Falconia
-
lunalcd2.pcb almost completeFri, 25 Jun 2021 22:31:24 +0000, by Mychaela Falconia
-
lunalcd2.pcb startedFri, 25 Jun 2021 20:29:36 +0000, by Mychaela Falconia
-
lunalcd2/src/Makefile: generate elements.pcbFri, 25 Jun 2021 19:11:21 +0000, by Mychaela Falconia
-
lunalcd2/src/Makefile: generate pcb-netlist.txtFri, 25 Jun 2021 19:08:13 +0000, by Mychaela Falconia
-
lunalcd2: MCL binding completeFri, 25 Jun 2021 19:01:35 +0000, by Mychaela Falconia
-
lunalcd2: structural Verilog source capturedFri, 25 Jun 2021 18:44:11 +0000, by Mychaela Falconia
-
lunalcd2: footprint for the DIP switch packFri, 25 Jun 2021 17:12:02 +0000, by Mychaela Falconia
-
lunalcd2 project started with MCLWed, 23 Jun 2021 23:53:15 +0000, by Mychaela Falconia
-
lunakpd1/README addedWed, 23 Jun 2021 08:44:43 +0000, by Mychaela Falconia
-
lunalcd[12]/README writtenWed, 23 Jun 2021 08:23:10 +0000, by Mychaela Falconia
-
lcr0402: add MakefileTue, 22 Jun 2021 05:27:16 +0000, by Mychaela Falconia
-
lcr0402 project startedTue, 22 Jun 2021 05:20:42 +0000, by Mychaela Falconia
-
duart28c/src/MCL: update for Digi-Key parts actually on orderSun, 02 Aug 2020 20:51:27 +0000, by Mychaela Falconia
-
duart28c/src/Makefile: U7.slotmap dependency was missedWed, 29 Jul 2020 15:53:57 +0000, by Mychaela Falconia
-
duart28c: new parts added to netlistWed, 29 Jul 2020 07:59:20 +0000, by Mychaela Falconia
-
duart28c/src/primitives: OD buffer pieces addedWed, 29 Jul 2020 07:30:45 +0000, by Mychaela Falconia
-
duart28c: 74LVC2G07 pinout capturedWed, 29 Jul 2020 07:27:14 +0000, by Mychaela Falconia
-
duart28c MCL: new components addedWed, 29 Jul 2020 07:21:04 +0000, by Mychaela Falconia
-
duart28c: started with a copy from duart28Wed, 29 Jul 2020 07:08:28 +0000, by Mychaela Falconia
-
duart28: another U5 slot changeTue, 28 Jul 2020 17:54:56 +0000, by Mychaela Falconia
-
duart28: U5 & U6 slot change by PCB layout engineerTue, 28 Jul 2020 17:01:37 +0000, by Mychaela Falconia
-
duart28/how-to-compile addedFri, 24 Jul 2020 23:27:57 +0000, by Mychaela Falconia
-
duart28/pcb: starting point for layout jobFri, 24 Jul 2020 23:23:42 +0000, by Mychaela Falconia
-
duart28/design-spec: layout instructions addedFri, 24 Jul 2020 20:22:36 +0000, by Mychaela Falconia
-
duart28/src/Makefile: added dependency on U[56].slotmapFri, 24 Jul 2020 20:21:54 +0000, by Mychaela Falconia
-
duart28/src/MCL: value attribute was wrong on the tantalum capFri, 24 Jul 2020 20:20:55 +0000, by Mychaela Falconia
-
duart28/design-spec: circuit description should be completeThu, 23 Jul 2020 19:49:00 +0000, by Mychaela Falconia
-
duart28/design-spec: re-measured partial power-down currentThu, 23 Jul 2020 18:14:16 +0000, by Mychaela Falconia
-
duart28/design-spec: coming alongThu, 23 Jul 2020 06:59:32 +0000, by Mychaela Falconia
-
duart28/design-spec: minor fixes in the so-far-written sectionTue, 14 Jul 2020 19:01:29 +0000, by Mychaela Falconia
-
duart28/design-spec startedTue, 14 Jul 2020 07:40:42 +0000, by Mychaela Falconia
-
duart28/src/Makefile: netlist MCL binding addedSun, 05 Jul 2020 00:10:45 +0000, by Mychaela Falconia
-
duart28 MCL: resistors capturedSat, 04 Jul 2020 23:37:47 +0000, by Mychaela Falconia
-
duart28: added bypass caps on FT2232D VCCIOA & VCCIOBSat, 04 Jul 2020 22:02:49 +0000, by Mychaela Falconia
-
duart28 MCL: capacitors capturedSat, 04 Jul 2020 21:50:10 +0000, by Mychaela Falconia
-
duart28: U5 & U6 preliminary slotmapsMon, 29 Jun 2020 03:15:08 +0000, by Mychaela Falconia
-
duart28: new design ideasSun, 28 Jun 2020 22:06:24 +0000, by Mychaela Falconia
-
duart28 MCL: ferrite bead definedSat, 13 Jun 2020 18:12:28 +0000, by Mychaela Falconia
-
duart28 MCL: crystal definedSat, 13 Jun 2020 17:46:18 +0000, by Mychaela Falconia
-
duart28 MCL: beginning of hier= mappingSat, 13 Jun 2020 06:57:04 +0000, by Mychaela Falconia
-
duart28/src/vsrc/board.v: aux_5V addedSat, 13 Jun 2020 06:46:05 +0000, by Mychaela Falconia
-
duart28: vsrc passes sverpSat, 13 Jun 2020 06:38:05 +0000, by Mychaela Falconia
-
duart28/src/primitives: adapted from fc-ujaSat, 13 Jun 2020 05:28:01 +0000, by Mychaela Falconia
-
duart28 MCL: added 2-pin header for misc-use 5VSat, 13 Jun 2020 05:18:55 +0000, by Mychaela Falconia
-
duart28 project startedSat, 13 Jun 2020 05:12:39 +0000, by Mychaela Falconia
-
lunakpd1/pcb/Makefile addedSat, 09 May 2020 08:13:26 +0000, by Mychaela Falconia
-
lunakpd1.pcb completeSat, 09 May 2020 08:08:42 +0000, by Mychaela Falconia