FreeCalypso > hg > fc-small-hw
graph
-
lunakpd1/README addedWed, 23 Jun 2021 08:44:43 +0000, by Mychaela Falconia
-
lunalcd[12]/README writtenWed, 23 Jun 2021 08:23:10 +0000, by Mychaela Falconia
-
lcr0402: add MakefileTue, 22 Jun 2021 05:27:16 +0000, by Mychaela Falconia
-
lcr0402 project startedTue, 22 Jun 2021 05:20:42 +0000, by Mychaela Falconia
-
duart28c/src/MCL: update for Digi-Key parts actually on orderSun, 02 Aug 2020 20:51:27 +0000, by Mychaela Falconia
-
duart28c/src/Makefile: U7.slotmap dependency was missedWed, 29 Jul 2020 15:53:57 +0000, by Mychaela Falconia
-
duart28c: new parts added to netlistWed, 29 Jul 2020 07:59:20 +0000, by Mychaela Falconia
-
duart28c/src/primitives: OD buffer pieces addedWed, 29 Jul 2020 07:30:45 +0000, by Mychaela Falconia
-
duart28c: 74LVC2G07 pinout capturedWed, 29 Jul 2020 07:27:14 +0000, by Mychaela Falconia
-
duart28c MCL: new components addedWed, 29 Jul 2020 07:21:04 +0000, by Mychaela Falconia
-
duart28c: started with a copy from duart28Wed, 29 Jul 2020 07:08:28 +0000, by Mychaela Falconia
-
duart28: another U5 slot changeTue, 28 Jul 2020 17:54:56 +0000, by Mychaela Falconia
-
duart28: U5 & U6 slot change by PCB layout engineerTue, 28 Jul 2020 17:01:37 +0000, by Mychaela Falconia
-
duart28/how-to-compile addedFri, 24 Jul 2020 23:27:57 +0000, by Mychaela Falconia
-
duart28/pcb: starting point for layout jobFri, 24 Jul 2020 23:23:42 +0000, by Mychaela Falconia
-
duart28/design-spec: layout instructions addedFri, 24 Jul 2020 20:22:36 +0000, by Mychaela Falconia
-
duart28/src/Makefile: added dependency on U[56].slotmapFri, 24 Jul 2020 20:21:54 +0000, by Mychaela Falconia
-
duart28/src/MCL: value attribute was wrong on the tantalum capFri, 24 Jul 2020 20:20:55 +0000, by Mychaela Falconia
-
duart28/design-spec: circuit description should be completeThu, 23 Jul 2020 19:49:00 +0000, by Mychaela Falconia
-
duart28/design-spec: re-measured partial power-down currentThu, 23 Jul 2020 18:14:16 +0000, by Mychaela Falconia
-
duart28/design-spec: coming alongThu, 23 Jul 2020 06:59:32 +0000, by Mychaela Falconia
-
duart28/design-spec: minor fixes in the so-far-written sectionTue, 14 Jul 2020 19:01:29 +0000, by Mychaela Falconia
-
duart28/design-spec startedTue, 14 Jul 2020 07:40:42 +0000, by Mychaela Falconia
-
duart28/src/Makefile: netlist MCL binding addedSun, 05 Jul 2020 00:10:45 +0000, by Mychaela Falconia
-
duart28 MCL: resistors capturedSat, 04 Jul 2020 23:37:47 +0000, by Mychaela Falconia
-
duart28: added bypass caps on FT2232D VCCIOA & VCCIOBSat, 04 Jul 2020 22:02:49 +0000, by Mychaela Falconia
-
duart28 MCL: capacitors capturedSat, 04 Jul 2020 21:50:10 +0000, by Mychaela Falconia
-
duart28: U5 & U6 preliminary slotmapsMon, 29 Jun 2020 03:15:08 +0000, by Mychaela Falconia
-
duart28: new design ideasSun, 28 Jun 2020 22:06:24 +0000, by Mychaela Falconia
-
duart28 MCL: ferrite bead definedSat, 13 Jun 2020 18:12:28 +0000, by Mychaela Falconia
-
duart28 MCL: crystal definedSat, 13 Jun 2020 17:46:18 +0000, by Mychaela Falconia
-
duart28 MCL: beginning of hier= mappingSat, 13 Jun 2020 06:57:04 +0000, by Mychaela Falconia
-
duart28/src/vsrc/board.v: aux_5V addedSat, 13 Jun 2020 06:46:05 +0000, by Mychaela Falconia
-
duart28: vsrc passes sverpSat, 13 Jun 2020 06:38:05 +0000, by Mychaela Falconia
-
duart28/src/primitives: adapted from fc-ujaSat, 13 Jun 2020 05:28:01 +0000, by Mychaela Falconia
-
duart28 MCL: added 2-pin header for misc-use 5VSat, 13 Jun 2020 05:18:55 +0000, by Mychaela Falconia
-
duart28 project startedSat, 13 Jun 2020 05:12:39 +0000, by Mychaela Falconia
-
lunakpd1/pcb/Makefile addedSat, 09 May 2020 08:13:26 +0000, by Mychaela Falconia
-
lunakpd1.pcb completeSat, 09 May 2020 08:08:42 +0000, by Mychaela Falconia
-
lunakpd1.pcb: keypad layout completeSat, 09 May 2020 06:40:15 +0000, by Mychaela Falconia
-
lunakpd1: beginning of sensible layoutSat, 09 May 2020 06:08:40 +0000, by Mychaela Falconia
-
lunakpd1 placetool writtenSat, 09 May 2020 05:11:54 +0000, by Mychaela Falconia
-
lunakpd1.pcb startedSat, 09 May 2020 04:00:24 +0000, by Mychaela Falconia
-
lunakpd1 project startedSat, 09 May 2020 00:38:07 +0000, by Mychaela Falconia
-
lunalcd1/pcb/Makefile addedFri, 03 Apr 2020 00:02:03 +0000, by Mychaela Falconia
-
lunalcd1.pcb: should be completeThu, 02 Apr 2020 23:26:47 +0000, by Mychaela Falconia
-
lunalcd1.pcb: layout started, close to completeThu, 02 Apr 2020 22:41:19 +0000, by Mychaela Falconia
-
lunalcd1: added pull-down resistor on BL_EN lineThu, 02 Apr 2020 18:25:19 +0000, by Mychaela Falconia
-
lunalcd1: updated footprint for LDO regulatorWed, 01 Apr 2020 21:14:56 +0000, by Mychaela Falconia
-
lunalcd1: backlight resistors changed to 38.3RWed, 01 Apr 2020 21:13:21 +0000, by Mychaela Falconia
-
lunalcd1/src/MCL: use new FPC connector + LCD module footprintWed, 01 Apr 2020 16:52:34 +0000, by Mychaela Falconia
-
lunalcd1 board project startedSun, 22 Mar 2020 03:19:38 +0000, by Mychaela Falconia
-
mmtb1/pcb: added Makefile for fab output generationTue, 10 Dec 2019 06:56:59 +0000, by Mychaela Falconia
-
mmtb1.pcb: silk text markings addedTue, 10 Dec 2019 06:51:02 +0000, by Mychaela Falconia
-
mmtb1.pcb: DRC fixed to passTue, 10 Dec 2019 06:12:04 +0000, by Mychaela Falconia
-
.hgignore added, based on freecalypso-schem versionMon, 21 Oct 2019 01:02:20 +0000, by Mychaela Falconia
-
fc-small-hw separated from old freecalypso-schem repoMon, 21 Oct 2019 00:53:38 +0000, by Mychaela Falconia