FreeCalypso > hg > fc-small-hw
graph
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lunalcd2/src/Makefile: generate elements.pcbFri, 25 Jun 2021 19:11:21 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate pcb-netlist.txtFri, 25 Jun 2021 19:08:13 +0000, by Mychaela Falconia
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lunalcd2: MCL binding completeFri, 25 Jun 2021 19:01:35 +0000, by Mychaela Falconia
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lunalcd2: structural Verilog source capturedFri, 25 Jun 2021 18:44:11 +0000, by Mychaela Falconia
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lunalcd2: footprint for the DIP switch packFri, 25 Jun 2021 17:12:02 +0000, by Mychaela Falconia
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lunalcd2 project started with MCLWed, 23 Jun 2021 23:53:15 +0000, by Mychaela Falconia
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lunakpd1/README addedWed, 23 Jun 2021 08:44:43 +0000, by Mychaela Falconia