Fri, 25 Jun 2021 19:11:21 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate elements.pcb
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Fri, 25 Jun 2021 19:08:13 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate pcb-netlist.txt
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Fri, 25 Jun 2021 19:01:35 +0000 |
Mychaela Falconia |
lunalcd2: MCL binding complete
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Fri, 25 Jun 2021 18:44:11 +0000 |
Mychaela Falconia |
lunalcd2: structural Verilog source captured
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Fri, 25 Jun 2021 17:12:02 +0000 |
Mychaela Falconia |
lunalcd2: footprint for the DIP switch pack
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Wed, 23 Jun 2021 23:53:15 +0000 |
Mychaela Falconia |
lunalcd2 project started with MCL
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Wed, 23 Jun 2021 08:44:43 +0000 |
Mychaela Falconia |
lunakpd1/README added
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