| Fri, 25 Jun 2021 19:11:21 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate elements.pcb
|
| Fri, 25 Jun 2021 19:08:13 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate pcb-netlist.txt
|
| Fri, 25 Jun 2021 19:01:35 +0000 |
Mychaela Falconia |
lunalcd2: MCL binding complete
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| Fri, 25 Jun 2021 18:44:11 +0000 |
Mychaela Falconia |
lunalcd2: structural Verilog source captured
|
| Fri, 25 Jun 2021 17:12:02 +0000 |
Mychaela Falconia |
lunalcd2: footprint for the DIP switch pack
|
| Wed, 23 Jun 2021 23:53:15 +0000 |
Mychaela Falconia |
lunalcd2 project started with MCL
|
| Wed, 23 Jun 2021 08:44:43 +0000 |
Mychaela Falconia |
lunakpd1/README added
|
| Wed, 23 Jun 2021 08:23:10 +0000 |
Mychaela Falconia |
lunalcd[12]/README written
|
| Tue, 22 Jun 2021 05:27:16 +0000 |
Mychaela Falconia |
lcr0402: add Makefile
|
| Tue, 22 Jun 2021 05:20:42 +0000 |
Mychaela Falconia |
lcr0402 project started
|
| Sun, 02 Aug 2020 20:51:27 +0000 |
Mychaela Falconia |
duart28c/src/MCL: update for Digi-Key parts actually on order
|
| Wed, 29 Jul 2020 15:53:57 +0000 |
Mychaela Falconia |
duart28c/src/Makefile: U7.slotmap dependency was missed
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| Wed, 29 Jul 2020 07:59:20 +0000 |
Mychaela Falconia |
duart28c: new parts added to netlist
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| Wed, 29 Jul 2020 07:30:45 +0000 |
Mychaela Falconia |
duart28c/src/primitives: OD buffer pieces added
|
