FreeCalypso > hg > fc-small-hw
graph
-
lunalcd2/pcb: add MakefileFri, 25 Jun 2021 23:08:00 +0000, by Mychaela Falconia
-
lunalcd2.pcb: manual DRC fixesFri, 25 Jun 2021 22:59:37 +0000, by Mychaela Falconia
-
lunalcd2.pcb complete except for DRCFri, 25 Jun 2021 22:52:20 +0000, by Mychaela Falconia
-
lunalcd2.pcb almost completeFri, 25 Jun 2021 22:31:24 +0000, by Mychaela Falconia
-
lunalcd2.pcb startedFri, 25 Jun 2021 20:29:36 +0000, by Mychaela Falconia
-
lunalcd2/src/Makefile: generate elements.pcbFri, 25 Jun 2021 19:11:21 +0000, by Mychaela Falconia
-
lunalcd2/src/Makefile: generate pcb-netlist.txtFri, 25 Jun 2021 19:08:13 +0000, by Mychaela Falconia
-
lunalcd2: MCL binding completeFri, 25 Jun 2021 19:01:35 +0000, by Mychaela Falconia
-
lunalcd2: structural Verilog source capturedFri, 25 Jun 2021 18:44:11 +0000, by Mychaela Falconia
-
lunalcd2: footprint for the DIP switch packFri, 25 Jun 2021 17:12:02 +0000, by Mychaela Falconia
-
lunalcd2 project started with MCLWed, 23 Jun 2021 23:53:15 +0000, by Mychaela Falconia
-
lunakpd1/README addedWed, 23 Jun 2021 08:44:43 +0000, by Mychaela Falconia
-
lunalcd[12]/README writtenWed, 23 Jun 2021 08:23:10 +0000, by Mychaela Falconia
-
lcr0402: add MakefileTue, 22 Jun 2021 05:27:16 +0000, by Mychaela Falconia
-
lcr0402 project startedTue, 22 Jun 2021 05:20:42 +0000, by Mychaela Falconia