log

age author description
Fri, 25 Jun 2021 23:08:00 +0000 Mychaela Falconia lunalcd2/pcb: add Makefile
Fri, 25 Jun 2021 22:59:37 +0000 Mychaela Falconia lunalcd2.pcb: manual DRC fixes
Fri, 25 Jun 2021 22:52:20 +0000 Mychaela Falconia lunalcd2.pcb complete except for DRC
Fri, 25 Jun 2021 22:31:24 +0000 Mychaela Falconia lunalcd2.pcb almost complete
Fri, 25 Jun 2021 20:29:36 +0000 Mychaela Falconia lunalcd2.pcb started
Fri, 25 Jun 2021 19:11:21 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate elements.pcb
Fri, 25 Jun 2021 19:08:13 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate pcb-netlist.txt
Fri, 25 Jun 2021 19:01:35 +0000 Mychaela Falconia lunalcd2: MCL binding complete
Fri, 25 Jun 2021 18:44:11 +0000 Mychaela Falconia lunalcd2: structural Verilog source captured
Fri, 25 Jun 2021 17:12:02 +0000 Mychaela Falconia lunalcd2: footprint for the DIP switch pack
Wed, 23 Jun 2021 23:53:15 +0000 Mychaela Falconia lunalcd2 project started with MCL
Wed, 23 Jun 2021 08:44:43 +0000 Mychaela Falconia lunakpd1/README added
Wed, 23 Jun 2021 08:23:10 +0000 Mychaela Falconia lunalcd[12]/README written
Tue, 22 Jun 2021 05:27:16 +0000 Mychaela Falconia lcr0402: add Makefile
Tue, 22 Jun 2021 05:20:42 +0000 Mychaela Falconia lcr0402 project started