log

age author description
Sat, 09 May 2020 06:08:40 +0000 Mychaela Falconia lunakpd1: beginning of sensible layout
Sat, 09 May 2020 05:11:54 +0000 Mychaela Falconia lunakpd1 placetool written
Sat, 09 May 2020 04:00:24 +0000 Mychaela Falconia lunakpd1.pcb started
Sat, 09 May 2020 00:38:07 +0000 Mychaela Falconia lunakpd1 project started
Fri, 03 Apr 2020 00:02:03 +0000 Mychaela Falconia lunalcd1/pcb/Makefile added
Thu, 02 Apr 2020 23:26:47 +0000 Mychaela Falconia lunalcd1.pcb: should be complete
Thu, 02 Apr 2020 22:41:19 +0000 Mychaela Falconia lunalcd1.pcb: layout started, close to complete
Thu, 02 Apr 2020 18:25:19 +0000 Mychaela Falconia lunalcd1: added pull-down resistor on BL_EN line
Wed, 01 Apr 2020 21:14:56 +0000 Mychaela Falconia lunalcd1: updated footprint for LDO regulator
Wed, 01 Apr 2020 21:13:21 +0000 Mychaela Falconia lunalcd1: backlight resistors changed to 38.3R
Wed, 01 Apr 2020 16:52:34 +0000 Mychaela Falconia lunalcd1/src/MCL: use new FPC connector + LCD module footprint
Sun, 22 Mar 2020 03:19:38 +0000 Mychaela Falconia lunalcd1 board project started
Tue, 10 Dec 2019 06:56:59 +0000 Mychaela Falconia mmtb1/pcb: added Makefile for fab output generation
Tue, 10 Dec 2019 06:51:02 +0000 Mychaela Falconia mmtb1.pcb: silk text markings added
Tue, 10 Dec 2019 06:12:04 +0000 Mychaela Falconia mmtb1.pcb: DRC fixed to pass