log

age author description
Wed, 02 Nov 2022 07:22:44 +0000 Mychaela Falconia sim-fpc-pasv/pcb: add Makefile for Gerber output default tip
Tue, 25 Oct 2022 07:31:52 +0000 Mychaela Falconia sim-fpc-pasv: PCB layout done
Tue, 25 Oct 2022 06:13:01 +0000 Mychaela Falconia sim-fpc-pasv: schem+BOM design complete
Tue, 25 Oct 2022 05:13:55 +0000 Mychaela Falconia sim-fpc-pasv MCL: FPC connector footprint
Tue, 25 Oct 2022 03:17:34 +0000 Mychaela Falconia sim-fpc-pasv: starting project with MCL
Sat, 04 Dec 2021 22:28:05 +0000 Mychaela Falconia lunalcd3: add Makefile for Gerber output generation
Thu, 18 Nov 2021 07:44:45 +0000 Mychaela Falconia lunalcd3.pcb: add orientation marker to U1
Thu, 18 Nov 2021 07:40:13 +0000 Mychaela Falconia lunalcd3.pcb: add orientation marker to SW1
Thu, 18 Nov 2021 06:55:23 +0000 Mychaela Falconia lunalcd3.pcb: layout changes around top bracket
Thu, 18 Nov 2021 06:45:36 +0000 Mychaela Falconia lunalcd3.pcb: extend ground plane for top bracket addition
Thu, 18 Nov 2021 06:44:24 +0000 Mychaela Falconia lunalcd3.pcb: add top bracket to LCD footprint
Thu, 18 Nov 2021 06:29:01 +0000 Mychaela Falconia lunalcd3.pcb: reroute LCD power trace around right ear of bottom bracket
Thu, 18 Nov 2021 06:11:27 +0000 Mychaela Falconia lunalcd3.pcb: manually add bottom strap to LCD footprint
Thu, 18 Nov 2021 04:59:47 +0000 Mychaela Falconia lunalcd3 project started
Sat, 26 Jun 2021 21:16:48 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate BOM outputs
Sat, 26 Jun 2021 21:16:08 +0000 Mychaela Falconia lunalcd2/src/MCL: resistor parts nailed down
Sat, 26 Jun 2021 20:40:29 +0000 Mychaela Falconia lunalcd2/src/MCL: different part for two-post VBAT supply header
Fri, 25 Jun 2021 23:08:00 +0000 Mychaela Falconia lunalcd2/pcb: add Makefile
Fri, 25 Jun 2021 22:59:37 +0000 Mychaela Falconia lunalcd2.pcb: manual DRC fixes
Fri, 25 Jun 2021 22:52:20 +0000 Mychaela Falconia lunalcd2.pcb complete except for DRC
Fri, 25 Jun 2021 22:31:24 +0000 Mychaela Falconia lunalcd2.pcb almost complete
Fri, 25 Jun 2021 20:29:36 +0000 Mychaela Falconia lunalcd2.pcb started
Fri, 25 Jun 2021 19:11:21 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate elements.pcb
Fri, 25 Jun 2021 19:08:13 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate pcb-netlist.txt
Fri, 25 Jun 2021 19:01:35 +0000 Mychaela Falconia lunalcd2: MCL binding complete
Fri, 25 Jun 2021 18:44:11 +0000 Mychaela Falconia lunalcd2: structural Verilog source captured
Fri, 25 Jun 2021 17:12:02 +0000 Mychaela Falconia lunalcd2: footprint for the DIP switch pack
Wed, 23 Jun 2021 23:53:15 +0000 Mychaela Falconia lunalcd2 project started with MCL