| Wed, 02 Nov 2022 07:22:44 +0000 |
Mychaela Falconia |
sim-fpc-pasv/pcb: add Makefile for Gerber output
default tip
|
| Tue, 25 Oct 2022 07:31:52 +0000 |
Mychaela Falconia |
sim-fpc-pasv: PCB layout done
|
| Tue, 25 Oct 2022 06:13:01 +0000 |
Mychaela Falconia |
sim-fpc-pasv: schem+BOM design complete
|
| Tue, 25 Oct 2022 05:13:55 +0000 |
Mychaela Falconia |
sim-fpc-pasv MCL: FPC connector footprint
|
| Tue, 25 Oct 2022 03:17:34 +0000 |
Mychaela Falconia |
sim-fpc-pasv: starting project with MCL
|
| Sat, 04 Dec 2021 22:28:05 +0000 |
Mychaela Falconia |
lunalcd3: add Makefile for Gerber output generation
|
| Thu, 18 Nov 2021 07:44:45 +0000 |
Mychaela Falconia |
lunalcd3.pcb: add orientation marker to U1
|
| Thu, 18 Nov 2021 07:40:13 +0000 |
Mychaela Falconia |
lunalcd3.pcb: add orientation marker to SW1
|
| Thu, 18 Nov 2021 06:55:23 +0000 |
Mychaela Falconia |
lunalcd3.pcb: layout changes around top bracket
|
| Thu, 18 Nov 2021 06:45:36 +0000 |
Mychaela Falconia |
lunalcd3.pcb: extend ground plane for top bracket addition
|
| Thu, 18 Nov 2021 06:44:24 +0000 |
Mychaela Falconia |
lunalcd3.pcb: add top bracket to LCD footprint
|
| Thu, 18 Nov 2021 06:29:01 +0000 |
Mychaela Falconia |
lunalcd3.pcb: reroute LCD power trace around right ear of bottom bracket
|
| Thu, 18 Nov 2021 06:11:27 +0000 |
Mychaela Falconia |
lunalcd3.pcb: manually add bottom strap to LCD footprint
|
| Thu, 18 Nov 2021 04:59:47 +0000 |
Mychaela Falconia |
lunalcd3 project started
|
| Sat, 26 Jun 2021 21:16:48 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate BOM outputs
|
| Sat, 26 Jun 2021 21:16:08 +0000 |
Mychaela Falconia |
lunalcd2/src/MCL: resistor parts nailed down
|
| Sat, 26 Jun 2021 20:40:29 +0000 |
Mychaela Falconia |
lunalcd2/src/MCL: different part for two-post VBAT supply header
|
| Fri, 25 Jun 2021 23:08:00 +0000 |
Mychaela Falconia |
lunalcd2/pcb: add Makefile
|
| Fri, 25 Jun 2021 22:59:37 +0000 |
Mychaela Falconia |
lunalcd2.pcb: manual DRC fixes
|
| Fri, 25 Jun 2021 22:52:20 +0000 |
Mychaela Falconia |
lunalcd2.pcb complete except for DRC
|
| Fri, 25 Jun 2021 22:31:24 +0000 |
Mychaela Falconia |
lunalcd2.pcb almost complete
|
| Fri, 25 Jun 2021 20:29:36 +0000 |
Mychaela Falconia |
lunalcd2.pcb started
|
| Fri, 25 Jun 2021 19:11:21 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate elements.pcb
|
| Fri, 25 Jun 2021 19:08:13 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate pcb-netlist.txt
|
| Fri, 25 Jun 2021 19:01:35 +0000 |
Mychaela Falconia |
lunalcd2: MCL binding complete
|
| Fri, 25 Jun 2021 18:44:11 +0000 |
Mychaela Falconia |
lunalcd2: structural Verilog source captured
|
| Fri, 25 Jun 2021 17:12:02 +0000 |
Mychaela Falconia |
lunalcd2: footprint for the DIP switch pack
|
| Wed, 23 Jun 2021 23:53:15 +0000 |
Mychaela Falconia |
lunalcd2 project started with MCL
|
| Wed, 23 Jun 2021 08:44:43 +0000 |
Mychaela Falconia |
lunakpd1/README added
|
| Wed, 23 Jun 2021 08:23:10 +0000 |
Mychaela Falconia |
lunalcd[12]/README written
|
| Tue, 22 Jun 2021 05:27:16 +0000 |
Mychaela Falconia |
lcr0402: add Makefile
|
| Tue, 22 Jun 2021 05:20:42 +0000 |
Mychaela Falconia |
lcr0402 project started
|
| Sun, 02 Aug 2020 20:51:27 +0000 |
Mychaela Falconia |
duart28c/src/MCL: update for Digi-Key parts actually on order
|
| Wed, 29 Jul 2020 15:53:57 +0000 |
Mychaela Falconia |
duart28c/src/Makefile: U7.slotmap dependency was missed
|
| Wed, 29 Jul 2020 07:59:20 +0000 |
Mychaela Falconia |
duart28c: new parts added to netlist
|
| Wed, 29 Jul 2020 07:30:45 +0000 |
Mychaela Falconia |
duart28c/src/primitives: OD buffer pieces added
|
| Wed, 29 Jul 2020 07:27:14 +0000 |
Mychaela Falconia |
duart28c: 74LVC2G07 pinout captured
|
| Wed, 29 Jul 2020 07:21:04 +0000 |
Mychaela Falconia |
duart28c MCL: new components added
|
| Wed, 29 Jul 2020 07:08:28 +0000 |
Mychaela Falconia |
duart28c: started with a copy from duart28
|
| Tue, 28 Jul 2020 17:54:56 +0000 |
Mychaela Falconia |
duart28: another U5 slot change
|
| Tue, 28 Jul 2020 17:01:37 +0000 |
Mychaela Falconia |
duart28: U5 & U6 slot change by PCB layout engineer
|
| Fri, 24 Jul 2020 23:27:57 +0000 |
Mychaela Falconia |
duart28/how-to-compile added
|
| Fri, 24 Jul 2020 23:23:42 +0000 |
Mychaela Falconia |
duart28/pcb: starting point for layout job
|
| Fri, 24 Jul 2020 20:22:36 +0000 |
Mychaela Falconia |
duart28/design-spec: layout instructions added
|
| Fri, 24 Jul 2020 20:21:54 +0000 |
Mychaela Falconia |
duart28/src/Makefile: added dependency on U[56].slotmap
|
| Fri, 24 Jul 2020 20:20:55 +0000 |
Mychaela Falconia |
duart28/src/MCL: value attribute was wrong on the tantalum cap
|
| Thu, 23 Jul 2020 19:49:00 +0000 |
Mychaela Falconia |
duart28/design-spec: circuit description should be complete
|
| Thu, 23 Jul 2020 18:14:16 +0000 |
Mychaela Falconia |
duart28/design-spec: re-measured partial power-down current
|
| Thu, 23 Jul 2020 06:59:32 +0000 |
Mychaela Falconia |
duart28/design-spec: coming along
|
| Tue, 14 Jul 2020 19:01:29 +0000 |
Mychaela Falconia |
duart28/design-spec: minor fixes in the so-far-written section
|
| Tue, 14 Jul 2020 07:40:42 +0000 |
Mychaela Falconia |
duart28/design-spec started
|
| Sun, 05 Jul 2020 00:10:45 +0000 |
Mychaela Falconia |
duart28/src/Makefile: netlist MCL binding added
|
| Sat, 04 Jul 2020 23:37:47 +0000 |
Mychaela Falconia |
duart28 MCL: resistors captured
|
| Sat, 04 Jul 2020 22:02:49 +0000 |
Mychaela Falconia |
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
|
| Sat, 04 Jul 2020 21:50:10 +0000 |
Mychaela Falconia |
duart28 MCL: capacitors captured
|
| Mon, 29 Jun 2020 03:15:08 +0000 |
Mychaela Falconia |
duart28: U5 & U6 preliminary slotmaps
|
