FreeCalypso > hg > fc-tourmaline

annotate src/cs/drivers/drv_app/r2d/uwire.h @ 273:5caa86ee2cfa

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enable L1_NEW_AEC in l1_confg.h (bold change) The AEC function implemented in DSP ROM 3606 on the Calypso silicon we work with is the one that corresponds to L1_NEW_AEC; the same holds for DSP 34 and even for DSP 33 with more recent patch versions. However, TI shipped their TCS211 reference fw with L1_NEW_AEC set to 0, thus driving AEC the old way if anyone tried to enable it, either via AT%Nxxxx or via the audio mode facility. As a result, the fw would try to control features which no longer exist in the DSP (long vs short echo and the old echo suppression level bits), while providing no way to tune the 8 new parameter words added to the DSP's NDB page. The only sensible solution is to bite the bullet and enable L1_NEW_AEC in L1 config, with fallout propagating into RiViera Audio Service T_AUDIO_AEC_CFG structure and into /aud/*.cfg binary file format. The latter fallout will be addressed in further code changes.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 29 Jul 2021 18:32:40 +0000
parents 4e78acac3d88
children
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /**
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2
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3 @file: uwire.h
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4
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5 @author Davide Carpegna
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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7 @version 1.0
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8
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9 Purpose: Driver for the uwire HD module
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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11 */
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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13 /*
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15 Date Modification
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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16 ------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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17 09/22/2000 Create
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18 10/18/2001 Updated for R2D by Christophe Favergeon
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20
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21 (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved
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22 */
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23
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24 #ifndef _UWIRE_H_
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25 #define _UWIRE_H_
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27 #define MEM_UWIRE 0xFFFE4000
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28 #define TDR (MEM_UWIRE)
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29 #define RDR (MEM_UWIRE)
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30 #define CSR (MEM_UWIRE+0x02)
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31 #define SR1 (MEM_UWIRE+0x04)
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32 #define SR2 (MEM_UWIRE+0x06)
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33 #define SR3 (MEM_UWIRE+0x08)
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34
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35 #define INDEX_CS1 (1 << 10)
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36 #define NB_BITS_WR_8 (1 << 8 )
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37 #define INDEX_CS0 0
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38 #define NB_BITS_WR_9 (9 << 5)
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39 #define CS_CMD (1 << 12)
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40 #define START (1 << 13)
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41 #define CS1_EDGE_RD (1 << 6)
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42 #define CS1_FRQ_FINT_4 (1 << 9)
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43 #define CS0_FRQ_FINT_2 0
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44 #define CS0_FRQ_FINT_4 (1 << 3)
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45 #define SR3_CLK_EN 1
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47 #define CSRB ( 1<<14 )
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49 #define IO_SEL0 0xFFFEF008
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50 #define IO_SEL 0xFFFEF00A
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52 #define GPIO_INOUT 0xFFFE4804
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53 #define GPIO_OUT 0xFFFE4802
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54 #define CNTL_RST 0xFFFFFD04
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55
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56 #ifdef _WINDOWS
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57 #ifdef __cplusplus
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58 extern "C"
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59 {
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60 #endif
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61 #endif
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62
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63 // prototypes of uwire functions for lcd
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64 BOOLEAN lcd_polling(void);
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65 void lcd_transmit_cmd(UINT8 cmd);
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66 void uwire_init_lcd(void);
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67
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68 // Defined only for board
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69 void lcd_transmit_data(UINT8 data);
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70
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71 // Defined only for PC
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72 void lcd_refresh(void);
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73 void lcd_set_pos(unsigned char x,unsigned char y);
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74 void* lcd_get_dc(void);
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75
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76 #ifdef _WINDOWS
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77 #ifdef __cplusplus
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78 }
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79 #endif
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80 #endif
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81
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82 #endif /*_UWIRE_H_*/