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comparison src/cs/layer1/include/l1_const.h @ 0:4e78acac3d88

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src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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-1:000000000000 0:4e78acac3d88
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONST.H
4 *
5 * Filename l1_const.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifdef __MSDOS__ // Running BORLANDC compiler.
11 #ifdef MVC
12 #define EXIT exit(0)
13 #define FAR
14 #else
15 #define EXIT DOS_Exit(0)
16 #define FAR far
17 #endif
18 #else // Running ARM compiler.
19 #define FAR
20 #define EXIT exit(0)
21 #define stricmp strcmp
22 #endif
23
24
25 #if (CODE_VERSION != SIMULATION)
26 #define NULL 0
27 #endif
28
29 #define NO_PAR 0
30
31 #define NO_TASK 0
32 #define ALL_TASK 0xffffffff
33 #define ALL_PARAM 0xffffffff
34
35 #define TRUE 1
36 #define TRUE_L 1L
37 #define FALSE 0
38
39 #define NOT_PENDING 0
40 #define PENDING 1
41
42 #define INACTIVE 2
43 #define ACTIVE 3
44 #define RE_ENTERED 4
45 #define WAIT_IQ 5
46
47 //---------------------------------------------
48 // MCU-DSP bit-field bit position definitions
49 //---------------------------------------------
50 #if L1_GPRS
51 #define GPRS_SCHEDULER 1 // Select GPRS scheduler
52 #endif
53 #define GSM_SCHEDULER 2 // Select GSM scheduler
54
55 //-----------------------------
56 // POWER MANAGEMENT............
57 //-----------------------------
58 #define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.setup_afc_and_rf) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(2)
59 #define TPU_LOAD 01
60 #define TPU_FREEZE 02
61
62 // SLEEP ALGO SWITCH
63 #define NO_SLEEP 00 // ------ + ------ + ------
64 #define SMALL_SLEEP 01 // SMALL + ------ + ------
65 #define BIG_SLEEP 02 // ------ + BIG + ------
66 #define DEEP_SLEEP 03 // ------ + BIG + DEEP
67 #define ALL_SLEEP 04 // SMALL + BIG + DEEP
68 #define BIG_SMALL_SLEEP 05 // SMALL + BIG + ------
69
70 // GAUGING SAMPLES
71 #define SIZE_HIST 10
72 #define MAX_BAD_GAUGING 3
73
74 // GAUG_IN_32T = (HF in clock of 13Mhz*dpll) * ( LF in Khz)
75 #define GAUG_IN_32T 1348 // gauging duration is 1348*T32 measured on eva4
76
77 // DSP state need to be used to enter Deep Sleep mode
78 #if (W_A_DSP_IDLE3 == 1)
79 #define C_DSP_IDLE3 3
80 #endif
81
82 //-------------------------------------------------
83 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
84 // to face temperature variation
85 //
86 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
87 // 9 frames gauging is 1348*T32 (measured on eva4)
88 // UPDATE: variation allowed is +- 6 ppm jitter
89 //-------------------------------------------------
90
91 #define MCUCLK 13000 // 13 Mhz
92 #define LF 32.768
93 #define LF_100PPM 32.7712768 // 32.768*(1+100*10E-6)
94 #define LF_500PPM 32.751616 // 32.768*(1-500*10E-6)
95 #define LF_50PPM 32.7696384 // 32.768*(1+50*10E-6)
96 #define LF_6PPM 32.76819661 // 32.768*(1+6*10E-6)
97
98 #define NB_INIT 5 // nbr of gauging to pass to ACQUIS
99 #define NB_ACQU 10 // nbr of gauging to pass to UPDATE
100
101 #if (CHIPSET ==2 || CHIPSET ==3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) // PLL is at 65 Mhz !!!!!!
102 #define PLL 5 // 5*13Mhz = 65 Mhz
103 //-------------------------------------------------
104 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
105 //
106 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
107 // 9 frames gauging is 1348*T32 (measured on eva4)
108 // UPDATE: variation allowed is +- 6 ppm jitter
109 //-------------------------------------------------
110 #define C_CLK_MIN 1983 // 65000/32.7712768 = 1983.444234
111 #define C_CLK_INIT_MIN 29113 // 0.444234*2^16
112 #define C_CLK_MAX 1984 // 65000 / 32.751616 = 1984.634896
113 #define C_CLK_INIT_MAX 41608 // 0.634896*2^16
114 #define C_DELTA_HF_ACQUIS 130 // 1348/32.768-1348/32.7696384 = 0.002056632ms
115 // 0.002056632/0.0001538 = 130 T65Mhz
116 #define C_DELTA_HF_UPDATE 15 // 1348/32.768-1348/32.76819661 =0.00024691ms
117 // 0.00024691/0.0001538 = 15 T65Mhz
118 #endif
119
120 #define ARMIO_CLK_CUT 0x0001
121 #define UWIRE_CLK_CUT 0x0002
122
123 //-----------------------------
124 // Neighbour cell sync. reading
125 //-----------------------------
126 #if (L1_12NEIGH)
127 #define NBR_NEIGHBOURS 12
128 #else
129 #define NBR_NEIGHBOURS 6
130 #endif
131
132 //-----------------------------
133 // LAYER 1 MEASUREMENT TASKS...
134 //-----------------------------
135 #define NBR_L1S_MEAS_TASKS 4
136
137 #define FSMS 0
138 #define I_BAMS 1
139 #define D_BAMS 2
140 #define SERVMS 3
141
142 #define FSMS_MEAS (TRUE_L << FSMS) // Measurement task on FULL list (Cell Selection/Idle).
143 #define I_BAMS_MEAS (TRUE_L << I_BAMS) // Measurement task on BA list in Idle.
144 #define D_BAMS_MEAS (TRUE_L << D_BAMS) // Measurement task on BA list in Dedicated.
145 #define SERVMS_MEAS (TRUE_L << SERVMS) // Measurement task for Serving.
146
147 #define FSMS_MEAS_MASK ALL_TASK ^ FSMS_MEAS
148 #define I_BAMS_MEAS_MASK ALL_TASK ^ I_BAMS_MEAS
149 #define D_BAMS_MEAS_MASK ALL_TASK ^ D_BAMS_MEAS
150 #define SERVMS_MEAS_MASK ALL_TASK ^ SERVMS_MEAS
151
152 #define A_D_BLEN 456 // SACCH/SDCCH data block length (GSM 5.01 $7)
153 #define TCH_FS_BLEN 378 // TCH FULL SPEECH block length
154 #define TCH_HS_BLEN 211 // TCH HALF SPEECH block length
155 #define TCH_F_D_BLEN 456 // FACCH, TCH_DATA block length
156
157 /*
158 * FreeCalypso Frankenstein: the following definition was not present in
159 * our TCS211 version and we had to pull it from the LoCosto version for
160 * l1_cmplx.c to compile. However, the comment in the place where it is
161 * used says that it "valuable for code running on target with DSP 3606."
162 */
163 #define MIN_ACCEPTABLE_SNR_FOR_SB 200 // threshold under which a SB shall be considered as not found
164
165 // Define max PM/TDMA according to DSP code and TPU RAM size
166 //----------------------------------------------------------
167
168 // NOTE: we should use a global variable initialized at L1 start and function of rx synth setup time.
169
170 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 4))
171
172 // TPU RAM size limitation
173
174 #define NB_MEAS_MAX 4
175 #define NB_MEAS_MAX_GPRS 4
176
177 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
178
179 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
180
181 // DSP code 33: upto 8 PMs with GSM and GPRS scheduler
182
183 #define NB_MEAS_MAX 8
184 #define NB_MEAS_MAX_GPRS 8
185
186 #elif (DSP == 32)
187
188 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
189 // and 8 PMs with GPRS scheduler, 6 for DSP 32 because of CPU load
190
191 #define NB_MEAS_MAX 4
192 #define NB_MEAS_MAX_GPRS 6
193
194 #else
195
196
197 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
198 // and 8 PMs with GPRS scheduler
199
200 #define NB_MEAS_MAX 4
201 #define NB_MEAS_MAX_GPRS 8
202
203 #endif
204 #endif
205 #if (AMR == 1)
206 #define SID_UPDATE_BLEN 212 // SID UPDATE block length
207 #define RATSCCH_BLEN 212 // RATSCCH block length
208 #define TCH_AFS_BLEN 448 // TCH Adaptative Full rate Speech block length
209 // Note: the d_nerr value is calculated thanks to the bit class 1 of the block.
210 // But the number AHS bit class 1 depends on the type of vocoder currently used (c.f. 5.03 &3.10.7.2)
211 #define TCH_AHS_7_95_BLEN 188 // TCH AHS 7.95 Speech block length
212 #define TCH_AHS_7_4_BLEN 196 // TCH AHS 7.4 Speech block length
213 #define TCH_AHS_6_7_BLEN 200 // TCH AHS 6.7 Speech block length
214 #define TCH_AHS_5_9_BLEN 208 // TCH AHS 5.9 Speech block length
215 #define TCH_AHS_5_15_BLEN 212 // TCH AHS 5.15 Speech block length
216 #define TCH_AHS_4_75_BLEN 212 // TCH AHS 4.75 Speech block length
217 #endif
218 //----------------------------------------
219 // LAYER 1 Asynchronous processes names...
220 //----------------------------------------
221 #if (TESTMODE) && !(L1_GPRS)
222 #if (AUDIO_TASK == 1)
223 #if (L1_GTT)
224 #if (OP_L1_STANDALONE == 1)
225 #define NBR_L1A_PROCESSES 45
226 #else
227 #define NBR_L1A_PROCESSES 44
228 #endif
229 #else
230 #if (OP_L1_STANDALONE == 1)
231 #define NBR_L1A_PROCESSES 44
232 #else
233 #define NBR_L1A_PROCESSES 43
234 #endif
235 #endif
236 #else
237 #if (L1_GTT)
238 #if (OP_L1_STANDALONE == 1)
239 #define NBR_L1A_PROCESSES 27
240 #else
241 #define NBR_L1A_PROCESSES 26
242 #endif
243 #else
244 #if (OP_L1_STANDALONE == 1)
245 #define NBR_L1A_PROCESSES 26
246 #else
247 #define NBR_L1A_PROCESSES 25
248 #endif
249 #endif
250 #endif
251 #endif
252
253 #if (TESTMODE) && (L1_GPRS)
254 #if (AUDIO_TASK == 1)
255 #if (L1_GTT)
256 #if (OP_L1_STANDALONE == 1)
257 #define NBR_L1A_PROCESSES 46
258 #else
259 #define NBR_L1A_PROCESSES 45
260 #endif
261 #else
262 #if (OP_L1_STANDALONE == 1)
263 #define NBR_L1A_PROCESSES 45
264 #else
265 #define NBR_L1A_PROCESSES 44
266 #endif
267 #endif
268 #else
269 #if (L1_GTT)
270 #if (OP_L1_STANDALONE == 1)
271 #define NBR_L1A_PROCESSES 28
272 #else
273 #define NBR_L1A_PROCESSES 27
274 #endif
275 #else
276 #if (OP_L1_STANDALONE == 1)
277 #define NBR_L1A_PROCESSES 27
278 #else
279 #define NBR_L1A_PROCESSES 26
280 #endif
281 #endif
282 #endif
283 #endif
284
285 #if !(TESTMODE)
286 #if (AUDIO_TASK == 1)
287 #if (L1_GTT)
288 #if (OP_L1_STANDALONE == 1)
289 #define NBR_L1A_PROCESSES 37
290 #else
291 #define NBR_L1A_PROCESSES 36
292 #endif
293 #else
294 #if (OP_L1_STANDALONE == 1)
295 #define NBR_L1A_PROCESSES 36
296 #else
297 #define NBR_L1A_PROCESSES 35
298 #endif
299 #endif
300 #else
301 #if (L1_GTT)
302 #if (OP_L1_STANDALONE == 1)
303 #define NBR_L1A_PROCESSES 19
304 #else
305 #define NBR_L1A_PROCESSES 18
306 #endif
307 #else
308 #if (OP_L1_STANDALONE == 1)
309 #define NBR_L1A_PROCESSES 18
310 #else
311 #define NBR_L1A_PROCESSES 17
312 #endif
313 #endif
314 #endif
315 #endif
316
317
318 #define FULL_MEAS 0 // l1a_full_list_meas_process(msg)
319 #define CS_NORM 1 // l1a_cs_bcch_process(msg)
320 #define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg)
321 #define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg)
322 #define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg)
323 #define I_SMSCB 5 // l1a_idle_smscb_process(msg)
324 #define CR_B 6 // l1a_cres_process(msg)
325 #define ACCESS 7 // l1a_access_process(msg)
326 #define DEDICATED 8 // l1a_dedicated_process(msg)
327 #define I_FULL_MEAS 9 // l1a_dedicated_process(msg)
328 #define I_NMEAS 10 // l1a_idle_ba_meas_process(msg)
329 #define DEDIC_6 11 // l1a_dedic6_process(msg)
330 #define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg)
331 #define HW_TEST 13 // l1a_test_process(msg)
332 #define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg)
333 #define I_ADC 15 // l1a_mmi_adc_req(msg)
334
335 #if (TESTMODE) && !(L1_GPRS)
336 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
337 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
338 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
339 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
340 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
341 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
342 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
343 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
344 #if (AUDIO_TASK == 1)
345 #define L1A_KEYBEEP_STATE 24 // l1a_mmi_keybeep_process(msg)
346 #define L1A_TONE_STATE 25 // l1a_mmi_tone_process(msg)
347 #define L1A_MELODY0_STATE 26 // l1a_mmi_melody0_process(msg)
348 #define L1A_MELODY1_STATE 27 // l1a_mmi_melody1_process(msg)
349 #define L1A_VM_PLAY_STATE 28 // l1a_mmi_vm_playing_process(msg)
350 #define L1A_VM_RECORD_STATE 29 // l1a_mmi_vm_recording_process(msg)
351 #define L1A_SR_ENROLL_STATE 30 // l1a_mmi_sr_enroll_process(msg)
352 #define L1A_SR_UPDATE_STATE 31 // l1a_mmi_sr_update_process(msg)
353 #define L1A_SR_RECO_STATE 32 // l1a_mmi_sr_reco_process(msg)
354 #define L1A_SR_UPDATE_CHECK_STATE 33 // l1a_mmi_sr_update_check_process(msg)
355 #define L1A_AEC_STATE 34 // l1a_mmi_aec_process(msg)
356 #define L1A_FIR_STATE 35 // l1a_mmi_fir_process(msg)
357 #define L1A_AUDIO_MODE_STATE 36 // l1a_mmi_audio_mode_process(msg)
358 #define L1A_MELODY0_E2_STATE 37 // l1a_mmi_melody0_e2_process(msg)
359 #define L1A_MELODY1_E2_STATE 38 // l1a_mmi_melody1_e2_process(msg)
360 #define L1A_VM_AMR_PLAY_STATE 39 // l1a_mmi_vm_amr_playing_process(msg)
361 #define L1A_VM_AMR_RECORD_STATE 40 // l1a_mmi_vm_amr_recording_process(msg)
362 #define L1A_CPORT_STATE 41 // l1a_mmi_cport_process(msg)
363 #if (L1_GTT == 1)
364 #define L1A_GTT_STATE 42 // l1a_mmi_gtt_process(msg)
365 #define INIT_L1 43 // l1a_init_layer1_process(msg)
366 #if (OP_L1_STANDALONE == 1)
367 #define HSW_CONF 44 // l1a_test_config_process(msg)
368 #endif
369 #else
370 #define INIT_L1 42 // l1a_init_layer1_process(msg)
371 #if (OP_L1_STANDALONE == 1)
372 #define HSW_CONF 43 // l1a_test_config_process(msg)
373 #endif
374 #endif
375 #else
376 #if (L1_GTT == 1)
377 #define L1A_GTT_STATE 24 // l1a_mmi_gtt_process(msg)
378 #define INIT_L1 25 // l1a_init_layer1_process(msg)
379 #if (OP_L1_STANDALONE == 1)
380 #define HSW_CONF 26 // l1a_test_config_process(msg)
381 #endif
382 #else
383 #define INIT_L1 24 // l1a_init_layer1_process(msg)
384 #if (OP_L1_STANDALONE == 1)
385 #define HSW_CONF 25 // l1a_test_config_process(msg)
386 #endif
387 #endif
388 #endif
389 #endif
390
391 #if (TESTMODE) && (L1_GPRS)
392 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
393 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
394 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
395 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
396 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
397 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
398 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
399 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
400 #define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg)
401 #if (AUDIO_TASK == 1)
402 #define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg)
403 #define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg)
404 #define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg)
405 #define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg)
406 #define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg)
407 #define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg)
408 #define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg)
409 #define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg)
410 #define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg)
411 #define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg)
412 #define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg)
413 #define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg)
414 #define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg)
415 #define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg)
416 #define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg)
417 #define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg)
418 #define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg)
419 #define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg)
420 #if (L1_GTT == 1)
421 #define L1A_GTT_STATE 43
422 #define INIT_L1 44 // l1a_init_layer1_process(msg)
423 #if (OP_L1_STANDALONE == 1)
424 #define HSW_CONF 45 // l1a_test_config_process(msg)
425 #endif
426 #else
427 #define INIT_L1 43 // l1a_init_layer1_process(msg)
428 #if (OP_L1_STANDALONE == 1)
429 #define HSW_CONF 44 // l1a_test_config_process(msg)
430 #endif
431 #endif
432 #else
433 #if (L1_GTT == 1)
434 #define L1A_GTT_STATE 25
435 #define INIT_L1 26 // l1a_init_layer1_process(msg)
436 #if (OP_L1_STANDALONE == 1)
437 #define HSW_CONF 27 // l1a_test_config_process(msg)
438 #endif
439 #else
440 #define INIT_L1 25 // l1a_init_layer1_process(msg)
441 #if (OP_L1_STANDALONE == 1)
442 #define HSW_CONF 26 // l1a_test_config_process(msg)
443 #endif
444 #endif
445 #endif
446 #endif
447
448 #if !(TESTMODE) && (AUDIO_TASK == 1)
449 #define L1A_KEYBEEP_STATE 16 // l1a_mmi_keybeep_process(msg)
450 #define L1A_TONE_STATE 17 // l1a_mmi_tone_process(msg)
451 #define L1A_MELODY0_STATE 18 // l1a_mmi_melody0_process(msg)
452 #define L1A_MELODY1_STATE 19 // l1a_mmi_melody1_process(msg)
453 #define L1A_VM_PLAY_STATE 20 // l1a_mmi_vm_playing_process(msg)
454 #define L1A_VM_RECORD_STATE 21 // l1a_mmi_vm_recording_process(msg)
455 #define L1A_SR_ENROLL_STATE 22 // l1a_mmi_sr_enroll_process(msg)
456 #define L1A_SR_UPDATE_STATE 23 // l1a_mmi_sr_update_process(msg)
457 #define L1A_SR_RECO_STATE 24 // l1a_mmi_sr_reco_process(msg)
458 #define L1A_SR_UPDATE_CHECK_STATE 25 // l1a_mmi_sr_update_check_process(msg)
459 #define L1A_AEC_STATE 26 // l1a_mmi_aec_process(msg)
460 #define L1A_FIR_STATE 27 // l1a_mmi_fir_process(msg)
461 #define L1A_AUDIO_MODE_STATE 28 // l1a_mmi_audio_mode_process(msg)
462 #define L1A_MELODY0_E2_STATE 29 // l1a_mmi_melody0_e2_process(msg)
463 #define L1A_MELODY1_E2_STATE 30 // l1a_mmi_melody1_e2_process(msg)
464 #define L1A_VM_AMR_PLAY_STATE 31 // l1a_mmi_vm_amr_playing_process(msg)
465 #define L1A_VM_AMR_RECORD_STATE 32 // l1a_mmi_vm_amr_recording_process(msg)
466 #define L1A_CPORT_STATE 33 // l1a_mmi_cport_process(msg)
467 #if (L1_GTT == 1)
468 #define L1A_GTT_STATE 34 // l1a_mmi_tty_process(msg)
469 #define INIT_L1 35 // l1a_init_layer1_process(msg)
470 #if (OP_L1_STANDALONE == 1)
471 #define HSW_CONF 36 // l1a_test_config_process(msg)
472 #endif
473 #else
474 #define INIT_L1 34 // l1a_init_layer1_process(msg)
475 #if (OP_L1_STANDALONE == 1)
476 #define HSW_CONF 35 // l1a_test_config_process(msg)
477 #endif
478 #endif
479 #elif !(TESTMODE) && !(AUDIO_TASK == 1)
480 #if (L1_GTT == 1)
481 #define L1A_GTT_STATE 16 // l1a_mmi_tty_process(msg)
482 #define INIT_L1 17 // l1a_init_layer1_process(msg)
483 #if (OP_L1_STANDALONE == 1)
484 #define HSW_CONF 18 // l1a_test_config_process(msg)
485 #endif
486 #else
487 #define INIT_L1 16 // l1a_init_layer1_process(msg)
488 #if (OP_L1_STANDALONE == 1)
489 #define HSW_CONF 17 // l1a_test_config_process(msg)
490 #endif
491 #endif
492 #endif
493
494 #if TESTMODE
495 #define TMODE_UPLINK (1<<0)
496 #define TMODE_DOWNLINK (1<<1)
497 #endif
498
499 //------------------------------------
500 // LAYER 1 DOWNLINK & UPLINK TASKS...
501 //------------------------------------
502 #define TASK_DISABLED 0
503 #define TASK_ENABLED 1
504
505 #define SEMAPHORE_RESET 0
506 #define SEMAPHORE_SET 1
507
508 #define NO_NEW_TASK -1
509
510
511 // Tasks in the order of their priority (low to high).
512
513 #if !L1_GPRS
514
515 #define NBR_DL_L1S_TASKS 32
516
517 //GSM_TASKS/
518 #define HWTEST 0 // DSP checksum reading
519 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
520 #define DEDIC 2 // Global Dedicated mode switch
521 #define RAACC 3 // Channel access (ul)
522 #define RAHO 4 // Handover access (ul)
523 #define NSYNC 5 // Global Neighbour cell synchro switch
524 #define FBNEW 6 // Frequency burst search (Idle mode)
525 #define SBCONF 7 // Synchro. burst confirmation
526 #define SB2 8 // Synchro. burst read (1 frame uncertainty / SB position)
527 #define FB26 9 // Frequency burst search, dedic/transfer mode MF26 or MF52
528 #define SB26 10 // Synchro burst search, dedic/transfer mode MF26 or MF52
529 #define SBCNF26 11 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
530 #define FB51 12 // Frequency burst search, dedic mode MF51
531 #define SB51 13 // Synchro burst search, dedic MF51
532 #define SBCNF51 14 // Synchro burst confirmation, dedic MF51
533 #define BCCHN 15 // BCCH Neighbor in GSM Idle
534 #define ALLC 16 // All CCCH Reading
535 #define EBCCHS 17 // Extended BCCH Serving Reading
536 #define NBCCHS 18 // Normal BCCH ServingReading
537 #define SMSCB 19 // CBCH serving Reading
538 #define NP 20 // Normal paging Reading
539 #define EP 21 // Extended pagingReading
540 #define ADL 22 // SACCH(SDCCH) DL
541 #define AUL 23 // SACCH(SDCCH) UL
542 #define DDL 24 // SDCCH DL
543 #define DUL 25 // SDCCH UL
544 #define TCHD 26 // Dummy for TCH Half rate
545 #define TCHA 27 // SACCH(TCH)
546 #define TCHTF 28 // TCH Full rate
547 #define TCHTH 29 // TCH Half rate
548 #define BCCHN_TOP 30 // BCCH Neighbour TOP priority in Idle mode
549 #define SYNCHRO 31 // synchro task: L1S reset
550 //END_GSM_TASKS/
551
552 #else
553
554 #define NBR_DL_L1S_TASKS 45
555
556 //GPRS_TASKS/
557 #define HWTEST 0 // DSP checksum reading
558 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
559 #define DEDIC 2 // Global Dedicated mode switch
560 #define RAACC 3 // Channel access (ul)
561 #define RAHO 4 // Handover access (ul)
562 #define NSYNC 5 // Global Neighbour cell synchro switch
563 #define POLL 6 // Packet Polling (Access)
564 #define PRACH 7 // Packet Random Access Channel
565 #define ITMEAS 8 // Interference measurements
566 #define FBNEW 9 // Frequency burst search (Idle mode)
567 #define SBCONF 10 // Synchro. burst confirmation
568 #define SB2 11 // Synchro. burst read (1 frame uncertainty / SB position)
569 #define PTCCH 12 // Packet Timing Advance control channel
570 #define FB26 13 // Frequency burst search, dedic/transfer mode MF26 or MF52
571 #define SB26 14 // Synchro burst search, dedic/transfer mode MF26 or MF52
572 #define SBCNF26 15 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
573 #define FB51 16 // Frequency burst search, dedic mode MF51
574 #define SB51 17 // Synchro burst search, dedic MF51
575 #define SBCNF51 18 // Synchro burst confirmation, dedic MF51
576 #define PDTCH 19 // Packet Data channel
577 #define BCCHN 20 // BCCH Neighbor in GSM Idle
578 #define ALLC 21 // All CCCH Reading
579 #define EBCCHS 22 // Extended BCCH Serving Reading
580 #define NBCCHS 23 // Normal BCCH Serving Reading
581 #define ADL 24 // SACCH(SDCCH) DL
582 #define AUL 25 // SACCH(SDCCH) UL
583 #define DDL 26 // SDCCH DL
584 #define DUL 27 // SDCCH UL
585 #define TCHD 28 // Dummy for TCH Half rate
586 #define TCHA 29 // SACCH(TCH)
587 #define TCHTF 30 // TCH Full rate
588 #define TCHTH 31 // TCH Half rate
589 #define PALLC 32 // All PCCCH reading
590 #define SMSCB 33 // CBCH serving Reading
591 #define PBCCHS 34 // PBCCH serving reading
592 #define PNP 35 // Packet Normal paging Reading
593 #define PEP 36 // Packet Extended paging Reading
594 #define SINGLE 37 // Single Block for GPRS
595 #define PBCCHN_TRAN 38 // Packet BCCH Neighbor in Packet Transfer mode.
596 #define PBCCHN_IDLE 39 // Packet BCCH Neighbor in Idle mode.
597 #define BCCHN_TRAN 40 // BCCH Neighbour in Packet Transfer mode
598 #define NP 41 // Normal paging Reading
599 #define EP 42 // Extended paging Reading
600 #define BCCHN_TOP 43 // BCCH Neighbour TOP priority in Idle mode
601 #define SYNCHRO 44 // synchro task: L1S reset
602 //END_GPRS_TASKS/
603
604 #endif
605
606 //------------------------------------
607 // LAYER 1 API
608 //------------------------------------
609 #define MCSI_PORT1 0
610 #define MCSI_PORT2 1
611
612
613 //---------------------------------
614 // DSP vocoder Enable/ Disable
615 //---------------------------------
616
617 #if (L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
618 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
619 #define TCH_VOCODER_DISABLE_REQ 0
620 #define TCH_VOCODER_ENABLE_REQ 1
621 #define TCH_VOCODER_ENABLED 2
622 #define TCH_VOCODER_DISABLED 3
623
624 // Number of TDMA wait frames until the DSP output is steady
625 #define DSP_VOCODER_ON_TRANSITION 165
626 #endif // FF_L1_TCH_VOCODER_CONTROL
627 #endif
628
629 //---------------------------------
630 // Handover Finished cause defines.
631 //---------------------------------
632 #define HO_COMPLETE 0
633 #define HO_TIMEOUT 1
634
635 //---------------------------------
636 // FB detection algorithm defines.
637 //---------------------------------
638 #define FB_MODE_0 0 // FB detec. mode 0.
639 #define FB_MODE_1 1 // FB detec. mode 1.
640
641 //---------------------------------
642 // AFC control defines.
643 //---------------------------------
644 #define AFC_INIT 1
645 #define AFC_OPEN_LOOP 2
646 #define AFC_CLOSED_LOOP 3
647
648 // For VCXO algo.
649 #if (VCXO_ALGO)
650 #define AFC_INIT_CENTER 4
651 #define AFC_INIT_MAX 5
652 #define AFC_INIT_MIN 6
653 #endif
654 //---------------------------------
655 // TOA control defines.
656 //---------------------------------
657 #define TOA_INIT 1
658 #define TOA_RUN 2
659
660 //---------------------------------
661 // Neighbour Synchro possible status.
662 //---------------------------------
663 #define NSYNC_FREE 0
664 #define NSYNC_PENDING 1
665 #define NSYNC_COMPLETED 2
666 #if (L1_12NEIGH ==1)
667 #define NSYNC_WAIT 3
668 #endif
669
670 /************************************/
671 /* Layer 1 constants declaration... */
672 /************************************/
673 #define MAX_FN ((UWORD32)26*51*2048)
674
675 #if L1_GPRS
676 #define MAX_BLOCK_ID ((UWORD32) (3 * (UWORD32) (MAX_FN / 13))) // Block ID corresponding to fn = FN MAX
677 #endif
678
679 //--------------------------------------------------------
680 // standard specific constants used in l1_config.std.xxx
681 //--------------------------------------------------------
682
683
684 // GSM
685 #define FIRST_ARFCN_GSM 1 // 1st arfcn is 1
686 #define NBMAX_CARRIER_GSM 124 // 124 for GSM, 174 for E_GSM, 374 for DCS1800.
687 #define MAX_TXPWR_GSM 19 // lowest power ctrl level value in GSM band
688 // GSM_E
689 #define FIRST_ARFCN_EGSM 1 // 1st arfcn is 1
690 #define NBMAX_CARRIER_EGSM 174 // 174 carriers for GSM_E.
691 #define MAX_TXPWR_EGSM 19 // lowest power ctrl level value in GSM-E band
692 // PCS1900
693 #define FIRST_ARFCN_PCS 512 // 1st arfcn is 512
694 #define NBMAX_CARRIER_PCS 299 // 299 carriers for PCS1900.
695 #define MAX_TXPWR_PCS 15 // lowest power ctrl level value in PCS band
696 #define TXPWR_TURNING_POINT_PCS 21
697 // DCS1800
698 #define FIRST_ARFCN_DCS 512 // 1st arfcn is 512
699 #define NBMAX_CARRIER_DCS 374 // 374 carriers for DCS1800.
700 #define MAX_TXPWR_DCS 15 // lowest power ctrl level value in DCS band
701 #define TXPWR_TURNING_POINT_DCS 28
702 // GSM850
703 #define FIRST_ARFCN_GSM850 128 // 1st arfcn is 128
704 #define NBMAX_CARRIER_GSM850 124 // 124 carriers for GSM850
705 #define NBMEAS_GSM850 3 // 3 measurement per frame TBD
706 #define MAX_TXPWR_GSM850 19 // lowest power ctrl level value in GSM band
707 // DUAL
708 #define FIRST_DCS_INDEX_DUAL 125 // 1st DCS index within the 498 continu list
709 #define NBMAX_CARRIER_DUAL 124+374 // 374 carriers for DCS1800 + 124 carriers for GSM900 Band
710 #define TXPWR_TURNING_POINT_DUAL 28
711 // DUALEXT
712 #define FIRST_DCS_INDEX_DUALEXT 175 // 1st DCS index within the 548 continu list
713 #define NBMAX_CARRIER_DUALEXT 174+374 // 374 carriers for DCS1800 + 174 carriers for E-GSM900 Band
714 #define TXPWR_TURNING_POINT_DUALEXT 28
715 // DUAL_US
716 #define FIRST_ARFCN_GSM850_DUAL_US 1 // 1st GSM850 index within the 423 continu list
717 #define FIRST_PCS_INDEX_DUAL_US 125 // 1st PCS index within the 423 continu list
718 #define NBMAX_CARRIER_DUAL_US 124+299 // 299 carriers for PCS1900 + 124 carriers for GSM850\ Band
719 #define NBMEAS_DUAL_US 4 // 4 measurements per frames.
720 #define TXPWR_TURNING_POINT_DUAL_US 28 // TBD
721
722
723 #define NBMAX_CARRIER NBMAX_CARRIER_DUALEXT //used in arrays for power measurement
724 //non optimized!!! (dynamic memory allocation to optimize)
725 #define BAND1 1
726 #define BAND2 2
727
728 #define NO_TXPWR 255 // sentinal value used with UWORD8 type.
729
730
731 //--------------------------------------------------------
732 // Receive level values.
733 //--------------------------------------------------------
734 #define RXLEV63 63 // max value for RXLEV.
735 #define IL_MIN 240 // minimum input level is -120 dbm.
736
737 //--------------------------------------------------------
738 // Max number of cell to report in MPHC_RXLEV_IND.
739 // Nb cells to check to see if cell of MPHC_NETWORK_SYNC_REQ has been detected
740 //--------------------------------------------------------
741 #define MAX_MEAS_RXLEV_IND_TRACE 10
742 #define NB_FQ_TO_CHK 4
743
744 /*--------------------------------------------------------*/
745 /* Max value for GSM Paging Parameters. */
746 /*--------------------------------------------------------*/
747 #define MAX_AG_BLKS_RES_NCOMB 7
748 #define MAX_AG_BLKS_RES_COMB 2
749 #define MAX_PG_BLOC_INDEX_NCOMB 8
750 #define MAX_PG_BLOC_INDEX_COMB 2
751 #define MAX_BS_PA_MFRMS 9
752
753 /*--------------------------------------------------------*/
754 /* Position of different blocs in a MF51. */
755 /*--------------------------------------------------------*/
756 #define NBCCH_POSITION 2 // Normal BCCH position in a MF51.
757 #define EBCCH_POSITION 6 // Extended BCCH position in a MF51.
758 #define CCCH_0 6
759 #define CCCH_1 12
760 #define CCCH_2 16
761 #define CCCH_3 22
762 #define CCCH_4 26
763 #define CCCH_5 32
764 #define CCCH_6 36
765 #define CCCH_7 42
766 #define CCCH_8 46
767 #define FB_0 0
768 #define FB_1 10
769 #define FB_2 20
770 #define FB_3 30
771 #define FB_4 40
772 #define SB_0 1
773 #define SB_1 11
774 #define SB_2 21
775 #define SB_3 31
776 #define SB_4 41
777
778 /*--------------------------------------------------------*/
779 /* System information position in the "si_bit_map". */
780 /*--------------------------------------------------------*/
781 #define SI_1 0x0001
782 #define SI_2 0x0002
783 #define SI_2BIS 0x0100
784 #define SI_2TER 0x0200
785 #define SI_3 0x0004
786 #define SI_4 0x0008
787 #define SI_7 0x0040
788 #define SI_8 0x0080
789 #define ALL_SI SI_1 | SI_2 | SI_2BIS | SI_2TER | SI_3 | SI_4 | SI_7 | SI_8
790
791 /*--------------------------------------------------------*/
792 /* CBCH position in the "smscb_bit_map". */
793 /*--------------------------------------------------------*/
794 #define CBCH_TB1 0x0001
795 #define CBCH_TB2 0x0002
796 #define CBCH_TB3 0x0004
797 #define CBCH_TB5 0x0008
798 #define CBCH_TB6 0x0010
799 #define CBCH_TB7 0x0020
800
801 #define CBCH_CONTINUOUS_READING 0
802 #define CBCH_SCHEDULED 1
803 #define CBCH_INACTIVE 2
804
805 /*--------------------------------------------------------*/
806 /* Channel type definitions for DEDICATED mode. */
807 /*--------------------------------------------------------*/
808
809 //TABLE/ CHAN TYPE
810 #define INVALID_CHANNEL 0
811 #define TCH_F 1
812 #define TCH_H 2
813 #define SDCCH_4 3
814 #define SDCCH_8 4
815 //END_TABLE/
816
817 /*--------------------------------------------------------*/
818 /* Channel mode definitions for DEDICATED. */
819 /*--------------------------------------------------------*/
820 #define SIG_ONLY_MODE 0 // signalling only
821 #define TCH_FS_MODE 1 // speech full rate
822 #define TCH_HS_MODE 2 // speech half rate
823 #define TCH_96_MODE 3 // data 9,6 kb/s
824 #define TCH_48F_MODE 4 // data 4,8 kb/s full rate
825 #define TCH_48H_MODE 5 // data 4,8 kb/s half rate
826 #define TCH_24F_MODE 6 // data 2,4 kb/s full rate
827 #define TCH_24H_MODE 7 // data 2,4 kb/s half rate
828 #define TCH_EFR_MODE 8 // enhanced full rate
829 #define TCH_144_MODE 9 // data 14,4 kb/s half rate
830 #if (AMR == 1)
831 #define TCH_AHS_MODE 10 // adaptative speech half rate
832 #define TCH_AFS_MODE 11 // adaptative speech full rate
833 #endif
834
835
836 /*--------------------------------------------------------*/
837 /* Layer 1 functional modes for "mode" setting pupose. */
838 /*--------------------------------------------------------*/
839 #define CS_MODE0 0 // functional mode at reset.
840 #define CS_MODE 1 // functional mode in CELL SELECTION.
841 #define I_MODE 2 // functional mode in IDLE.
842 #define CON_EST_MODE1 3 // functional mode in ACCESS (before 1st RA, for TOA convergency).
843 #define CON_EST_MODE2 4 // functional mode in ACCESS (after 1st RA).
844 #define DEDIC_MODE 5 // functional mode in DEDICATED.
845 #define DEDIC_MODE_HALF_DATA 6 // used only for TOA histogram length purpose.
846 #if L1_GPRS
847 #define PACKET_TRANSFER_MODE 7
848 #endif
849
850 /*--------------------------------------------------------*/
851 /* Error causes for MPHC_NO_BCCH message. */
852 /*--------------------------------------------------------*/
853 #define NO_FB_SB 0 // FB or SB not found.
854 #define NCC_NOT_PERMITTED 1 // Synchro OK! but PLMN not permitted.
855
856 /*--------------------------------------------------------*/
857 /* MFTAB constants and flags. */
858 /*--------------------------------------------------------*/
859 #define L1_MAX_FCT 5 /* Max number of fctions in a frame */
860 #define MFTAB_SIZE 20
861
862 /********************************/
863 /* Software register/flags */
864 /* definitions. */
865 /********************************/
866 #define NO_CTRL (TRUE_L << 0)
867 #define CTRL_MS (TRUE_L << 1)
868 #define CTRL_TX (TRUE_L << 2)
869 #define CTRL_RX (TRUE_L << 3)
870 #define CTRL_ADC (TRUE_L << 4)
871 #define CTRL_SYNC (TRUE_L << 5)
872 #define CTRL_ABORT (TRUE_L << 6)
873 #define CTRL_TEST (TRUE_L << 7)
874 #define CTRL_SYCB (TRUE_L << 8)
875 #define CTRL_FB_ABORT (TRUE_L << 9)
876 #if L1_GPRS
877 #define CTRL_PRACH (TRUE_L << 10)
878 #define CTRL_SYSINGLE (TRUE_L << 11)
879 #endif
880
881
882 /********************************/
883 /* MISC management */
884 /********************************/
885 #define GSM_CTL 0 // DSP ctrl for a GSM task
886 #define MISC_CTL 1 // DSP ctrl for a MISC task
887 #define GSM_MISC_CTL 2 // DSP ctrl for a GSM and MISC tasks
888
889 /********************************/
890 /* TOA management */
891 /********************************/
892 #define ISH_INVALID 128 // value used to disable the toa offset
893
894 /********************************/
895 /* AGC management */
896 /********************************/
897 #define DPAGC_FIFO_LEN 4
898 #define DPAGC_MAX_FLAG 1
899 #if (AMR == 1)
900 #define DPAGC_AMR_FIFO_LEN 4
901 #endif
902
903 /********************************/
904 /* ADC management */
905 /********************************/
906 #define ADC_DISABLED 0x0000
907 // Traffic part
908 #define ADC_MASK_RESET_TRAFFIC 0xFF00
909 #define ADC_NEXT_TRAFFIC_UL 0x0001
910 #define ADC_EACH_TRAFFIC_UL 0x0002
911 #define ADC_NEXT_TRAFFIC_DL 0x0004
912 #define ADC_EACH_TRAFFIC_DL 0x0008
913 #define ADC_EACH_RACH 0x0010
914
915
916 // Idle part
917 #define ADC_MASK_RESET_IDLE 0x00FF
918 #define ADC_NEXT_NORM_PAGING 0x0100
919 #define ADC_EACH_NORM_PAGING 0x0200
920 #define ADC_NEXT_MEAS_SESSION 0x0400
921 #define ADC_EACH_MEAS_SESSION 0x0800
922 #define ADC_NEXT_NORM_PAGING_REORG 0x1000
923 #define ADC_EACH_NORM_PAGING_REORG 0x2000
924
925
926 // CS_MODE0 part
927 #define ADC_NEXT_CS_MODE0 0x4000
928 #define ADC_EACH_CS_MODE0 0x8000
929
930
931 /********************************/
932 /* Neighbor BCCH priorities */
933 /********************************/
934
935 #define TOP_PRIORITY 0
936 #define HIGH_PRIORITY 1
937 #define NORMAL_PRIORITY 2
938
939 /********************************/
940 /* Driver constants definitions */
941 /********************************/
942
943 // Used to identify the 1st and last burst for offset management in Drivers.
944 #define BURST_1 0
945 #define BURST_2 1
946 #define BURST_3 2
947 #define BURST_4 3
948
949
950 // Identifier for all DSP tasks.
951 // ...RX & TX tasks identifiers.
952 #define NO_DSP_TASK 0 // No task.
953 #define NP_DSP_TASK 21 // Normal Paging reading task.
954 #define EP_DSP_TASK 22 // Extended Paging reading task.
955 #define NBS_DSP_TASK 19 // Normal BCCH serving reading task.
956 #define EBS_DSP_TASK 20 // Extended BCCH serving reading task.
957 #define NBN_DSP_TASK 17 // Normal BCCH neighbour reading task.
958 #define EBN_DSP_TASK 18 // Extended BCCH neighbour reading task.
959 #define ALLC_DSP_TASK 24 // CCCH reading task while performing FULL BCCH/CCCH reading task.
960 #define CB_DSP_TASK 25 // CBCH reading task.
961 #define DDL_DSP_TASK 26 // SDCCH/D (data) reading task.
962 #define ADL_DSP_TASK 27 // SDCCH/A (SACCH) reading task.
963 #define DUL_DSP_TASK 12 // SDCCH/D (data) transmit task.
964 #define AUL_DSP_TASK 11 // SDCCH/A (SACCH) transmit task.
965 #define RACH_DSP_TASK 10 // RACH transmit task.
966 #define TCHT_DSP_TASK 13 // TCH Traffic data DSP task id (RX or TX)
967 #define TCHA_DSP_TASK 14 // TCH SACCH data DSP task id (RX or TX)
968 #define TCHD_DSP_TASK 28 // TCH Traffic data DSP task id (RX or TX)
969
970 #define TCH_DTX_UL 15 // Replace UL task in DSP->MCU com. to say "burst not transmitted".
971
972 #if (L1_GPRS)
973 // Identifier for DSP tasks Packet dedicated.
974 // ...RX & TX tasks identifiers.
975 //------------------------------------------------------------------------
976 // WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
977 //------------------------------------------------------------------------
978 #define PNP_DSP_TASK 30
979 #define PEP_DSP_TASK 31
980 #define PALLC_DSP_TASK 32
981 #define PBS_DSP_TASK 33
982
983 #define PTCCH_DSP_TASK 33
984
985 #endif
986
987 // Identifier for measurement, FB / SB search tasks.
988 // Values 1,2,3 reserved for "number of measurements".
989 #define FB_DSP_TASK 5 // Freq. Burst reading task in Idle mode.
990 #define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode.
991 #define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode.
992 #define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode.
993 #define IDLE1 1
994
995 // Debug tasks
996 #define CHECKSUM_DSP_TASK 33
997 #define TST_NDB 35 // Checksum DSP->MCU
998 #define TST_DB 36 // DB communication check
999 #define INIT_VEGA 37
1000 #define DSP_LOOP_C 38
1001
1002 // Identifier for measurement, FB / SB search tasks.
1003 // Values 1,2,3 reserved for "number of measurements".
1004 #define TCH_LOOP_A 31
1005 #define TCH_LOOP_B 32
1006
1007 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1008 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800)))
1009 #else
1010 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x09A0 - 0x800)))
1011 #endif
1012
1013 // bits in d_gsm_bgd_mgt - background task management
1014 #define B_DSPBGD_RECO 1 // start of reco in dsp background
1015 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background
1016 #define B_DSPBGD_STOP_RECO 256 // stop of reco in dsp background
1017 #define B_DSPBGD_STOP_UPD 512 // stop of alignement update in dsp background
1018
1019 // bit in d_pll_config
1020 #define B_32KHZ_CALIB (TRUE_L << 14) // force DSP in Idle1 during 32 khz calibration
1021 // ****************************************************************
1022 // NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1023 // ****************************************************************
1024 // bits in d_tch_mode
1025 #define B_EOTD (TRUE_L << 0) // EOTD mode
1026 #define B_PLAY_UL (TRUE_L << 3) // Play UL
1027 #define B_DCO_ON (TRUE_L << 4) // DCO ON/OFF
1028 #define B_AUDIO_ASYNC (TRUE_L << 1) // WCP reserved
1029
1030 // ****************************************************************
1031 // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1032 // ****************************************************************
1033 #define C_POND_RED 1L
1034 // below values are defined in the file l1_time.h
1035 //#define D_NSUBB_IDLE 296L
1036 //#define D_NSUBB_DEDIC 30L
1037 #define D_FB_THR_DET_IACQ 0x3333L
1038 #define D_FB_THR_DET_TRACK 0x28f6L
1039 #define D_DC_OFF_THRES 0x7fffL
1040 #define D_DUMMY_THRES 17408L
1041 #define D_DEM_POND_GEWL 26624L
1042 #define D_DEM_POND_RED 20152L
1043 #define D_HOLE 0L
1044 #define D_TRANSFER_RATE 0x6666L
1045
1046 // Full Rate vocoder definitions.
1047 #define D_MACCTHRESH1 7872L
1048 #define D_MLDT -4L
1049 #define D_MACCTHRESH 7872L
1050 #define D_GU 5772L
1051 #define D_GO 7872L
1052 #define D_ATTMAX 53L
1053 #define D_SM -892L
1054 #define D_B 208L
1055 #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
1056 #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
1057 #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
1058 #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
1059
1060 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1061 // Frequency burst definitions
1062 #define D_FB_MARGIN_BEG 24
1063 #define D_FB_MARGIN_END 22
1064
1065 // V42bis definitions
1066 #define D_V42B_SWITCH_HYST 16L
1067 #define D_V42B_SWITCH_MIN 64L
1068 #define D_V42B_SWITCH_MAX 250L
1069 #define D_V42B_RESET_DELAY 10L
1070
1071 // Latencies definitions
1072 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1073 // C.f. BUG1404
1074 #define D_LAT_MCU_BRIDGE 0x000FL
1075 #else
1076 #define D_LAT_MCU_BRIDGE 0x0009L
1077 #endif
1078
1079 #define D_LAT_MCU_HOM2SAM 0x000CL
1080
1081 #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
1082 #define D_LAT_DSP_AFTER_SAM 0x0004L
1083
1084 // Background Task in GSM mode: Initialization.
1085 #define D_GSM_BGD_MGT 0L
1086
1087 #if (CHIPSET == 4)
1088 #define D_MISC_CONFIG 0L
1089 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
1090 #define D_MISC_CONFIG 1L
1091 #else
1092 #define D_MISC_CONFIG 0L
1093 #endif
1094
1095 #endif
1096
1097 // Hall Rate vocoder and ched definitions.
1098
1099 #define D_SD_MIN_THR_TCHHS 37L
1100 #define D_MA_MIN_THR_TCHHS 344L
1101 #define D_MD_MAX_THR_TCHHS 2175L
1102 #define D_MD1_MAX_THR_TCHHS 138L
1103 #define D_SD_AV_THR_TCHHS 1845L
1104 #define D_WED_FIL_TC 0x7c00L
1105 #define D_WED_FIL_INI 4650L
1106 #define D_X_MIN 15L
1107 #define D_X_MAX 23L
1108 #define D_Y_MIN 703L
1109 #define D_Y_MAX 2460L
1110 #define D_SLOPE 135L
1111 #define D_WED_DIFF_THRESHOLD 406L
1112 #define D_MABFI_MIN_THR_TCHHS 5320L
1113 #define D_LDT_HR -5
1114 #define D_MACCTRESH_HR 6500
1115 #define D_MACCTRESH1_HR 6500
1116 #define D_GU_HR 2620
1117 #define D_GO_HR 3700
1118 #define D_B_HR 182
1119 #define D_SM_HR -1608
1120 #define D_ATTMAX_HR 53
1121
1122 // Enhanced Full Rate vocoder and ched definitions.
1123
1124 #define C_MLDT_EFR -4
1125 #define C_MACCTHRESH_EFR 8000
1126 #define C_MACCTHRESH1_EFR 8000
1127 #define C_GU_EFR 4522
1128 #define C_GO_EFR 6500
1129 #define C_B_EFR 174
1130 #define C_SM_EFR -878
1131 #define C_ATTMAX_EFR 53
1132 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
1133 #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
1134 #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
1135 #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
1136
1137
1138 // Integrated Data Services definitions.
1139 #define D_MAX_OVSPD_UL 8
1140 // Detect frames containing 90% of 1s as synchro frames
1141 #define D_SYNC_THRES 0x3f50
1142 // IDLE frames are only frames with 100 % of 1s
1143 #define D_IDLE_THRES 0x4000
1144 #define D_M1_THRES 5
1145 #define D_MAX_OVSP_DL 8
1146
1147 // d_ra_act: bit field definition
1148 #define B_F48BLK 5
1149
1150 // Mask for b_itc information (d_ra_conf)
1151 #define CE_MASK 0x04
1152
1153 #define D_FACCH_THR 0
1154 #define D_DSP_TEST 0
1155 #define D_VERSION_NUMBER 0
1156 #define D_TI_VERSION 0
1157
1158
1159 /*------------------------------------------------------------------------------*/
1160 /* */
1161 /* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
1162 /* ++++++++++++++++++++++++++++++++++++++++++ */
1163 /* */
1164 /*------------------------------------------------------------------------------*/
1165 // COMMUNICATION Interrupt definition
1166 //------------------------------------
1167 #define ALL_16BIT 0xffffL
1168 #define B_GSM_PAGE (TRUE_L << 0)
1169 #define B_GSM_TASK (TRUE_L << 1)
1170 #define B_MISC_PAGE (TRUE_L << 2)
1171 #define B_MISC_TASK (TRUE_L << 3)
1172
1173 #define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
1174 #define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
1175 #define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
1176 #define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
1177
1178 // Common definition
1179 //----------------------------------
1180 // Index to *_DEMOD* arrays.
1181 #define D_TOA 0 // Time Of Arrival.
1182 #define D_PM 1 // Power Measurement.
1183 #define D_ANGLE 2 // Angle (AFC correction)
1184 #define D_SNR 3 // Signal / Noise Ratio.
1185
1186 // Bit name/position definitions.
1187 #define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
1188 #define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
1189 #define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
1190 #define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
1191 #define B_AF 14 // Activity bit: 1 if data block is valid.
1192 #define B_BFI 2 // Bad Frame Indicator
1193 #define B_UFI 0 // UNRELIABLE FRAME Indicator
1194 #define B_ECRC 9 // Enhanced full rate CRC bit
1195 #define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
1196
1197 #if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
1198 #define FACCH_GOOD 10
1199 #define FACCH_BAD 11
1200 #endif
1201
1202 #if (AMR == 1)
1203 // Place of the RX type in the AMR block header
1204 #define RX_TYPE_SHIFT 3
1205 #define RX_TYPE_MASK 0x0038
1206
1207 // Place of the vocoder type in the AMR block header
1208 #define VOCODER_TYPE_SHIFT 0
1209 #define VOCODER_TYPE_MASK 0x0007
1210
1211 // List of the possible RX types in a_dd block
1212 #define SPEECH_GOOD 0
1213 #define SPEECH_DEGRADED 1
1214 #define ONSET 2
1215 #define SPEECH_BAD 3
1216 #define SID_FIRST 4
1217 #define SID_UPDATE 5
1218 #define SID_BAD 6
1219 #define AMR_NO_DATA 7
1220 #define AMR_INHIBIT 8
1221
1222 // List of possible RX types in RATSCCH block
1223 #define C_RATSCCH_GOOD 5
1224
1225 // List of the possible AMR channel rate
1226 #define AMR_CHANNEL_4_75 0
1227 #define AMR_CHANNEL_5_15 1
1228 #define AMR_CHANNEL_5_9 2
1229 #define AMR_CHANNEL_6_7 3
1230 #define AMR_CHANNEL_7_4 4
1231 #define AMR_CHANNEL_7_95 5
1232 #define AMR_CHANNEL_10_2 6
1233 #define AMR_CHANNEL_12_2 7
1234
1235 // Types of RATSCCH blocks
1236 #define C_RATSCCH_UNKNOWN 0
1237 #define C_RATSCCH_CMI_PHASE_REQ 1
1238 #define C_RATSCCH_AMR_CONFIG_REQ_MAIN 2
1239 #define C_RATSCCH_AMR_CONFIG_REQ_ALT 3
1240 #define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4 // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
1241 #define C_RATSCCH_THRES_REQ 5
1242
1243 // These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
1244 #define C_AMR_CHANGE_CMIP 0
1245 #define C_AMR_CHANGE_ACS 1
1246 #define C_AMR_CHANGE_ICM 2
1247 #define C_AMR_CHANGE_THR1 3
1248 #define C_AMR_CHANGE_THR2 4
1249 #define C_AMR_CHANGE_THR3 5
1250 #define C_AMR_CHANGE_HYST1 6
1251 #define C_AMR_CHANGE_HYST2 7
1252 #define C_AMR_CHANGE_HYST3 8
1253
1254 // CMIP default value
1255 #define C_AMR_CMIP_DEFAULT 1 // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
1256
1257 #endif
1258 // "d_ctrl_tch" bits positions for TCH configuration.
1259 #define B_CHAN_MODE 0
1260 #define B_CHAN_TYPE 4
1261 #define B_RESET_SACCH 6
1262 #define B_VOCODER_ON 7
1263 #define B_SYNC_TCH_UL 8
1264 #if (AMR == 1)
1265 #define B_SYNC_AMR 9
1266 #else
1267 #define B_SYNC_TCH_DL 9
1268 #endif
1269 #define B_STOP_TCH_UL 10
1270 #define B_STOP_TCH_DL 11
1271 #define B_TCH_LOOP 12
1272 #define B_SUBCHANNEL 15
1273
1274 // "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
1275 #define B_RAMP 0
1276 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1277 #define B_BULRAMPDEL 3 // Note: this name is changed
1278 #define B_BULRAMPDEL2 2 // Note: this name is changed
1279 #define B_BULRAMPDEL_BIS 9
1280 #define B_BULRAMPDEL2_BIS 10
1281 #endif
1282 #define B_AFC 4
1283
1284 // "d_ctrl_system" bits positions.
1285 #define B_TSQ 0
1286 #define B_BCCH_FREQ_IND 3
1287 #define B_TASK_ABORT 15 // Abort RF tasks for DSP.
1288
1289 /*
1290 * FreeCalypso Frankenstein: the following definition has been
1291 * imported from LoCosto version of l1_const.h; it is needed for
1292 * the LoCosto-based C code to compile.
1293 */
1294 #define C_BA_PM_MEAS (2)
1295
1296 // ****************************************************************
1297 // POLESTAR EVABOARD 3 REGISTERS & ADRESSES DEFINITIONS
1298 // ****************************************************************
1299
1300
1301 // DSP ADRESSES
1302 //--------------------
1303
1304 #define DB_SIZE (4*20L) // 4 pages of 20 words...
1305
1306 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1307 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1308 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1309 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1310 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1311 #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words
1312 #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words
1313
1314 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1315 #define DB2_R_PAGE_0 0xFFD00184L
1316 #define DB2_R_PAGE_1 0xFFD00188L
1317 #endif
1318 #else
1319 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1320 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1321 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1322 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1323 #define NDB_ADR 0xFFD000a0L // NDB start address : 268 words
1324 #define PARAM_ADR 0xFFD002b8L // PARAM start address : 57 words
1325 #endif
1326
1327 // ****************************************************************
1328 // ADC reading definitions
1329 // ****************************************************************
1330
1331 #define ADC_READ_PERIOD (40) //30 * 4.615 = 140ms
1332
1333
1334 // ****************************************************************
1335 // AGC: IL table identifier used by function Cust_get_agc_from_IL
1336 // ****************************************************************
1337 #define MAX_ID 1
1338 #define AV_ID 2
1339 #define PWR_ID 3
1340
1341 #if TESTMODE
1342 // ****************************************************************
1343 // Testmode: State of the continous mode
1344 // ****************************************************************
1345 #define TM_NO_CONTINUOUS 1 // continuous mode isn't active
1346 #define TM_START_RX_CONTINUOUS 2 // start the Rx continuous mode
1347 #define TM_START_TX_CONTINUOUS 3 // start the Tx continuous mode
1348 #define TM_CONTINUOUS 4 // Rx or Tx continuous mode
1349 #endif
1350 #if (AMR == 1)
1351 // ****************************************************************
1352 // AMR: Position of each AMR parameters in the AMR API buffer
1353 // ****************************************************************
1354 #define NSCB_INDEX 0
1355 #define NSCB_SHIFT 6
1356 #define ICMUL_INDEX 0
1357 #define ICMUL_SHIFT 4
1358 #define ICMDL_INDEX 0
1359 #define ICMDL_SHIFT 1
1360 #define ICMIUL_INDEX 0
1361 #define ICMIUL_SHIFT 3
1362 #define ICMIDL_INDEX 0
1363 #define ICMIDL_SHIFT 0
1364 #define ACSUL_INDEX 1
1365 #define ACSUL_SHIFT 0
1366 #define ACSDL_INDEX 1
1367 #define ACSDL_SHIFT 8
1368 #define THR1_INDEX 2
1369 #define THR1_SHIFT 0
1370 #define THR2_INDEX 2
1371 #define THR2_SHIFT 6
1372 #define THR3_INDEX 3
1373 #define THR3_SHIFT 8
1374 #define HYST1_INDEX 3
1375 #define HYST1_SHIFT 0
1376 #define HYST2_INDEX 3
1377 #define HYST2_SHIFT 4
1378 #define HYST3_INDEX 2
1379 #define HYST3_SHIFT 12
1380 #define NSYNC_INDEX 3
1381 #define NSYNC_SHIFT 14
1382 #define CMIP_INDEX 3
1383 #define CMIP_SHIFT 15
1384
1385 #define NSCB_MASK 0x0001
1386 #define ICM_MASK 0x0003
1387 #define ICMI_MASK 0x0001
1388 #define ACS_MASK 0x00FF
1389 #define THR_MASK 0x003F
1390 #define HYST_MASK 0x000F
1391 #define CMIP_MASK 0x0001
1392 #endif
1393