FreeCalypso > hg > fc-tourmaline
view src/cs/layer1/p_include/l1p_vare.h @ 268:f2e52cab0a73
abb_inth.c: check all interrupt causes, not just one
The original code used if - else if - else if etc constructs, thus
the first detected interrupt was the only one handled. However,
Iota ITSTATREG is a clear-on-read register, thus if we only handle
the first detected interrupt and skip checking the others, then the
other interrupts will be lost, if more than one interrupt happened
to occur in one ABB interrupt handling cycle - a form of rare race
condition. Change the code to check all interrupts that were read
in this cycle.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 13 Jun 2021 18:17:53 +0000 (2021-06-13) |
| parents | 4e78acac3d88 |
| children |
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/************* Revision Controle System Header ************* * GSM Layer 1 software * L1P_VAREX.H * * Filename l1p_vare.h * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #ifdef L1P_ASYN_C #if (LONG_JUMP == 3) #ifdef __GNUC__ #define SECTION_ATTR __attribute__ ((section (".l1s_global"))) #else #define SECTION_ATTR #pragma DATA_SECTION(l1ps,".l1s_global") #pragma DATA_SECTION(l1pa_l1ps_com,".l1s_global") #pragma DATA_SECTION(l1ps_macs_com,".l1s_global") #pragma DATA_SECTION(l1ps_dsp_com,".l1s_global") #endif #else #define SECTION_ATTR #endif // Global Packet L1A structure T_L1PA_GLOBAL l1pa; // Global Packet L1S structure T_L1PS_GLOBAL l1ps SECTION_ATTR; // Common structure between L1A and L1S in packet mode T_L1PA_L1PS_COM l1pa_l1ps_com SECTION_ATTR; // Communication between L1S and MAC-S in packet mode T_L1PS_MACS_COM l1ps_macs_com SECTION_ATTR; // MCU / DSP interface T_L1PS_DSP_COM l1ps_dsp_com SECTION_ATTR; #undef SECTION_ATTR #else extern T_L1PA_GLOBAL l1pa; extern T_L1PS_GLOBAL l1ps; extern T_L1PA_L1PS_COM l1pa_l1ps_com; extern T_L1PS_DSP_COM l1ps_dsp_com; extern T_L1PS_MACS_COM l1ps_macs_com; #endif