annotate libftmini/ftdi_defs.h @ 56:842cff427588

cp2102: fix Intel HEX read/write bugs
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 11 Sep 2023 19:52:28 +0000
parents c53dee063cdd
children
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1 /*
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2 * This header file contains definitions for various bits that are fixed
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3 * in FTDI chips themselves. These definitions have been lifted from
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4 * libftdi-0.20 by Intra2net AG.
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5 */
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7 /** MPSSE bitbang modes */
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8 enum ftdi_mpsse_mode
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9 {
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10 BITMODE_RESET = 0x00, /**< switch off bitbang mode, back to regular serial/FIFO */
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11 BITMODE_BITBANG= 0x01, /**< classical asynchronous bitbang mode, introduced with B-type chips */
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12 BITMODE_MPSSE = 0x02, /**< MPSSE mode, available on 2232x chips */
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13 BITMODE_SYNCBB = 0x04, /**< synchronous bitbang mode, available on 2232x and R-type chips */
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14 BITMODE_MCU = 0x08, /**< MCU Host Bus Emulation mode, available on 2232x chips */
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15 /* CPU-style fifo mode gets set via EEPROM */
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16 BITMODE_OPTO = 0x10, /**< Fast Opto-Isolated Serial Interface Mode, available on 2232x chips */
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17 BITMODE_CBUS = 0x20, /**< Bitbang on CBUS pins of R-type chips, configure in EEPROM before */
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18 BITMODE_SYNCFF = 0x40, /**< Single Channel Synchronous FIFO mode, available on 2232H chips */
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19 };
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21 /** Port interface for chips with multiple interfaces */
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22 enum ftdi_interface
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23 {
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24 INTERFACE_ANY = 0,
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25 INTERFACE_A = 1,
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26 INTERFACE_B = 2,
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27 INTERFACE_C = 3,
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28 INTERFACE_D = 4
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29 };
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31 /* Shifting commands IN MPSSE Mode*/
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32 #define MPSSE_WRITE_NEG 0x01 /* Write TDI/DO on negative TCK/SK edge*/
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33 #define MPSSE_BITMODE 0x02 /* Write bits, not bytes */
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34 #define MPSSE_READ_NEG 0x04 /* Sample TDO/DI on negative TCK/SK edge */
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35 #define MPSSE_LSB 0x08 /* LSB first */
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36 #define MPSSE_DO_WRITE 0x10 /* Write TDI/DO */
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37 #define MPSSE_DO_READ 0x20 /* Read TDO/DI */
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38 #define MPSSE_WRITE_TMS 0x40 /* Write TMS/CS */
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40 /* FTDI MPSSE commands */
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41 #define SET_BITS_LOW 0x80
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42 /*BYTE DATA*/
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43 /*BYTE Direction*/
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44 #define SET_BITS_HIGH 0x82
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45 /*BYTE DATA*/
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46 /*BYTE Direction*/
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47 #define GET_BITS_LOW 0x81
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48 #define GET_BITS_HIGH 0x83
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49 #define LOOPBACK_START 0x84
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50 #define LOOPBACK_END 0x85
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51 #define TCK_DIVISOR 0x86
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52 /* H Type specific commands */
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53 #define DIS_DIV_5 0x8a
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54 #define EN_DIV_5 0x8b
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55 #define EN_3_PHASE 0x8c
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56 #define DIS_3_PHASE 0x8d
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57 #define CLK_BITS 0x8e
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58 #define CLK_BYTES 0x8f
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59 #define CLK_WAIT_HIGH 0x94
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60 #define CLK_WAIT_LOW 0x95
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61 #define EN_ADAPTIVE 0x96
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62 #define DIS_ADAPTIVE 0x97
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63 #define CLK_BYTES_OR_HIGH 0x9c
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64 #define CLK_BYTES_OR_LOW 0x0d
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65 /*FT232H specific commands */
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66 #define DRIVE_OPEN_COLLECTOR 0x9e
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67 /* Value Low */
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68 /* Value HIGH */ /*rate is 12000000/((1+value)*2) */
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69 #define DIV_VALUE(rate) (rate > 6000000)?0:((6000000/rate -1) > 0xffff)? 0xffff: (6000000/rate -1)
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71 /* Commands in MPSSE and Host Emulation Mode */
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72 #define SEND_IMMEDIATE 0x87
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73 #define WAIT_ON_HIGH 0x88
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74 #define WAIT_ON_LOW 0x89
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76 /* Commands in Host Emulation Mode */
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77 #define READ_SHORT 0x90
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78 /* Address_Low */
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79 #define READ_EXTENDED 0x91
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80 /* Address High */
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81 /* Address Low */
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82 #define WRITE_SHORT 0x92
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83 /* Address_Low */
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84 #define WRITE_EXTENDED 0x93
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85 /* Address High */
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86 /* Address Low */
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87
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88 /* Definitions for flow control */
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89 #define SIO_RESET 0 /* Reset the port */
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90 #define SIO_MODEM_CTRL 1 /* Set the modem control register */
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91 #define SIO_SET_FLOW_CTRL 2 /* Set flow control register */
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92 #define SIO_SET_BAUD_RATE 3 /* Set baud rate */
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93 #define SIO_SET_DATA 4 /* Set the data characteristics of the port */
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94
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95 #define FTDI_DEVICE_OUT_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_OUT)
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96 #define FTDI_DEVICE_IN_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_IN)
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98 /* Requests */
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99 #define SIO_RESET_REQUEST SIO_RESET
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100 #define SIO_SET_BAUDRATE_REQUEST SIO_SET_BAUD_RATE
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101 #define SIO_SET_DATA_REQUEST SIO_SET_DATA
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102 #define SIO_SET_FLOW_CTRL_REQUEST SIO_SET_FLOW_CTRL
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103 #define SIO_SET_MODEM_CTRL_REQUEST SIO_MODEM_CTRL
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104 #define SIO_POLL_MODEM_STATUS_REQUEST 0x05
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105 #define SIO_SET_EVENT_CHAR_REQUEST 0x06
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106 #define SIO_SET_ERROR_CHAR_REQUEST 0x07
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107 #define SIO_SET_LATENCY_TIMER_REQUEST 0x09
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108 #define SIO_GET_LATENCY_TIMER_REQUEST 0x0A
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109 #define SIO_SET_BITMODE_REQUEST 0x0B
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110 #define SIO_READ_PINS_REQUEST 0x0C
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111 #define SIO_READ_EEPROM_REQUEST 0x90
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112 #define SIO_WRITE_EEPROM_REQUEST 0x91
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113 #define SIO_ERASE_EEPROM_REQUEST 0x92
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114
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115 #define SIO_RESET_SIO 0
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116 #define SIO_RESET_PURGE_RX 1
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117 #define SIO_RESET_PURGE_TX 2
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118
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119 #define SIO_DISABLE_FLOW_CTRL 0x0
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120 #define SIO_RTS_CTS_HS (0x1 << 8)
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121 #define SIO_DTR_DSR_HS (0x2 << 8)
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122 #define SIO_XON_XOFF_HS (0x4 << 8)
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123
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124 #define SIO_SET_DTR_MASK 0x1
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125 #define SIO_SET_DTR_HIGH ( 1 | ( SIO_SET_DTR_MASK << 8))
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126 #define SIO_SET_DTR_LOW ( 0 | ( SIO_SET_DTR_MASK << 8))
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127 #define SIO_SET_RTS_MASK 0x2
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128 #define SIO_SET_RTS_HIGH ( 2 | ( SIO_SET_RTS_MASK << 8 ))
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129 #define SIO_SET_RTS_LOW ( 0 | ( SIO_SET_RTS_MASK << 8 ))
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130
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131 #define SIO_RTS_CTS_HS (0x1 << 8)