FreeCalypso > hg > fc-usbser-tools
changeset 13:c53dee063cdd
libftmini/ftdi_defs.h: extract from libftdi-0.20/src/ftdi.h
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Thu, 07 Sep 2023 07:19:43 +0000 |
parents | 80e521d6609c |
children | 67ecb394b24f |
files | libftmini/ftdi_defs.h |
diffstat | 1 files changed, 131 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/libftmini/ftdi_defs.h Thu Sep 07 07:19:43 2023 +0000 @@ -0,0 +1,131 @@ +/* + * This header file contains definitions for various bits that are fixed + * in FTDI chips themselves. These definitions have been lifted from + * libftdi-0.20 by Intra2net AG. + */ + +/** MPSSE bitbang modes */ +enum ftdi_mpsse_mode +{ + BITMODE_RESET = 0x00, /**< switch off bitbang mode, back to regular serial/FIFO */ + BITMODE_BITBANG= 0x01, /**< classical asynchronous bitbang mode, introduced with B-type chips */ + BITMODE_MPSSE = 0x02, /**< MPSSE mode, available on 2232x chips */ + BITMODE_SYNCBB = 0x04, /**< synchronous bitbang mode, available on 2232x and R-type chips */ + BITMODE_MCU = 0x08, /**< MCU Host Bus Emulation mode, available on 2232x chips */ + /* CPU-style fifo mode gets set via EEPROM */ + BITMODE_OPTO = 0x10, /**< Fast Opto-Isolated Serial Interface Mode, available on 2232x chips */ + BITMODE_CBUS = 0x20, /**< Bitbang on CBUS pins of R-type chips, configure in EEPROM before */ + BITMODE_SYNCFF = 0x40, /**< Single Channel Synchronous FIFO mode, available on 2232H chips */ +}; + +/** Port interface for chips with multiple interfaces */ +enum ftdi_interface +{ + INTERFACE_ANY = 0, + INTERFACE_A = 1, + INTERFACE_B = 2, + INTERFACE_C = 3, + INTERFACE_D = 4 +}; + +/* Shifting commands IN MPSSE Mode*/ +#define MPSSE_WRITE_NEG 0x01 /* Write TDI/DO on negative TCK/SK edge*/ +#define MPSSE_BITMODE 0x02 /* Write bits, not bytes */ +#define MPSSE_READ_NEG 0x04 /* Sample TDO/DI on negative TCK/SK edge */ +#define MPSSE_LSB 0x08 /* LSB first */ +#define MPSSE_DO_WRITE 0x10 /* Write TDI/DO */ +#define MPSSE_DO_READ 0x20 /* Read TDO/DI */ +#define MPSSE_WRITE_TMS 0x40 /* Write TMS/CS */ + +/* FTDI MPSSE commands */ +#define SET_BITS_LOW 0x80 +/*BYTE DATA*/ +/*BYTE Direction*/ +#define SET_BITS_HIGH 0x82 +/*BYTE DATA*/ +/*BYTE Direction*/ +#define GET_BITS_LOW 0x81 +#define GET_BITS_HIGH 0x83 +#define LOOPBACK_START 0x84 +#define LOOPBACK_END 0x85 +#define TCK_DIVISOR 0x86 +/* H Type specific commands */ +#define DIS_DIV_5 0x8a +#define EN_DIV_5 0x8b +#define EN_3_PHASE 0x8c +#define DIS_3_PHASE 0x8d +#define CLK_BITS 0x8e +#define CLK_BYTES 0x8f +#define CLK_WAIT_HIGH 0x94 +#define CLK_WAIT_LOW 0x95 +#define EN_ADAPTIVE 0x96 +#define DIS_ADAPTIVE 0x97 +#define CLK_BYTES_OR_HIGH 0x9c +#define CLK_BYTES_OR_LOW 0x0d +/*FT232H specific commands */ +#define DRIVE_OPEN_COLLECTOR 0x9e +/* Value Low */ +/* Value HIGH */ /*rate is 12000000/((1+value)*2) */ +#define DIV_VALUE(rate) (rate > 6000000)?0:((6000000/rate -1) > 0xffff)? 0xffff: (6000000/rate -1) + +/* Commands in MPSSE and Host Emulation Mode */ +#define SEND_IMMEDIATE 0x87 +#define WAIT_ON_HIGH 0x88 +#define WAIT_ON_LOW 0x89 + +/* Commands in Host Emulation Mode */ +#define READ_SHORT 0x90 +/* Address_Low */ +#define READ_EXTENDED 0x91 +/* Address High */ +/* Address Low */ +#define WRITE_SHORT 0x92 +/* Address_Low */ +#define WRITE_EXTENDED 0x93 +/* Address High */ +/* Address Low */ + +/* Definitions for flow control */ +#define SIO_RESET 0 /* Reset the port */ +#define SIO_MODEM_CTRL 1 /* Set the modem control register */ +#define SIO_SET_FLOW_CTRL 2 /* Set flow control register */ +#define SIO_SET_BAUD_RATE 3 /* Set baud rate */ +#define SIO_SET_DATA 4 /* Set the data characteristics of the port */ + +#define FTDI_DEVICE_OUT_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_OUT) +#define FTDI_DEVICE_IN_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_IN) + +/* Requests */ +#define SIO_RESET_REQUEST SIO_RESET +#define SIO_SET_BAUDRATE_REQUEST SIO_SET_BAUD_RATE +#define SIO_SET_DATA_REQUEST SIO_SET_DATA +#define SIO_SET_FLOW_CTRL_REQUEST SIO_SET_FLOW_CTRL +#define SIO_SET_MODEM_CTRL_REQUEST SIO_MODEM_CTRL +#define SIO_POLL_MODEM_STATUS_REQUEST 0x05 +#define SIO_SET_EVENT_CHAR_REQUEST 0x06 +#define SIO_SET_ERROR_CHAR_REQUEST 0x07 +#define SIO_SET_LATENCY_TIMER_REQUEST 0x09 +#define SIO_GET_LATENCY_TIMER_REQUEST 0x0A +#define SIO_SET_BITMODE_REQUEST 0x0B +#define SIO_READ_PINS_REQUEST 0x0C +#define SIO_READ_EEPROM_REQUEST 0x90 +#define SIO_WRITE_EEPROM_REQUEST 0x91 +#define SIO_ERASE_EEPROM_REQUEST 0x92 + +#define SIO_RESET_SIO 0 +#define SIO_RESET_PURGE_RX 1 +#define SIO_RESET_PURGE_TX 2 + +#define SIO_DISABLE_FLOW_CTRL 0x0 +#define SIO_RTS_CTS_HS (0x1 << 8) +#define SIO_DTR_DSR_HS (0x2 << 8) +#define SIO_XON_XOFF_HS (0x4 << 8) + +#define SIO_SET_DTR_MASK 0x1 +#define SIO_SET_DTR_HIGH ( 1 | ( SIO_SET_DTR_MASK << 8)) +#define SIO_SET_DTR_LOW ( 0 | ( SIO_SET_DTR_MASK << 8)) +#define SIO_SET_RTS_MASK 0x2 +#define SIO_SET_RTS_HIGH ( 2 | ( SIO_SET_RTS_MASK << 8 )) +#define SIO_SET_RTS_LOW ( 0 | ( SIO_SET_RTS_MASK << 8 )) + +#define SIO_RTS_CTS_HS (0x1 << 8)