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comparison libftmini/ftdi_defs.h @ 13:c53dee063cdd

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libftmini/ftdi_defs.h: extract from libftdi-0.20/src/ftdi.h
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 07 Sep 2023 07:19:43 +0000
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12:80e521d6609c 13:c53dee063cdd
1 /*
2 * This header file contains definitions for various bits that are fixed
3 * in FTDI chips themselves. These definitions have been lifted from
4 * libftdi-0.20 by Intra2net AG.
5 */
6
7 /** MPSSE bitbang modes */
8 enum ftdi_mpsse_mode
9 {
10 BITMODE_RESET = 0x00, /**< switch off bitbang mode, back to regular serial/FIFO */
11 BITMODE_BITBANG= 0x01, /**< classical asynchronous bitbang mode, introduced with B-type chips */
12 BITMODE_MPSSE = 0x02, /**< MPSSE mode, available on 2232x chips */
13 BITMODE_SYNCBB = 0x04, /**< synchronous bitbang mode, available on 2232x and R-type chips */
14 BITMODE_MCU = 0x08, /**< MCU Host Bus Emulation mode, available on 2232x chips */
15 /* CPU-style fifo mode gets set via EEPROM */
16 BITMODE_OPTO = 0x10, /**< Fast Opto-Isolated Serial Interface Mode, available on 2232x chips */
17 BITMODE_CBUS = 0x20, /**< Bitbang on CBUS pins of R-type chips, configure in EEPROM before */
18 BITMODE_SYNCFF = 0x40, /**< Single Channel Synchronous FIFO mode, available on 2232H chips */
19 };
20
21 /** Port interface for chips with multiple interfaces */
22 enum ftdi_interface
23 {
24 INTERFACE_ANY = 0,
25 INTERFACE_A = 1,
26 INTERFACE_B = 2,
27 INTERFACE_C = 3,
28 INTERFACE_D = 4
29 };
30
31 /* Shifting commands IN MPSSE Mode*/
32 #define MPSSE_WRITE_NEG 0x01 /* Write TDI/DO on negative TCK/SK edge*/
33 #define MPSSE_BITMODE 0x02 /* Write bits, not bytes */
34 #define MPSSE_READ_NEG 0x04 /* Sample TDO/DI on negative TCK/SK edge */
35 #define MPSSE_LSB 0x08 /* LSB first */
36 #define MPSSE_DO_WRITE 0x10 /* Write TDI/DO */
37 #define MPSSE_DO_READ 0x20 /* Read TDO/DI */
38 #define MPSSE_WRITE_TMS 0x40 /* Write TMS/CS */
39
40 /* FTDI MPSSE commands */
41 #define SET_BITS_LOW 0x80
42 /*BYTE DATA*/
43 /*BYTE Direction*/
44 #define SET_BITS_HIGH 0x82
45 /*BYTE DATA*/
46 /*BYTE Direction*/
47 #define GET_BITS_LOW 0x81
48 #define GET_BITS_HIGH 0x83
49 #define LOOPBACK_START 0x84
50 #define LOOPBACK_END 0x85
51 #define TCK_DIVISOR 0x86
52 /* H Type specific commands */
53 #define DIS_DIV_5 0x8a
54 #define EN_DIV_5 0x8b
55 #define EN_3_PHASE 0x8c
56 #define DIS_3_PHASE 0x8d
57 #define CLK_BITS 0x8e
58 #define CLK_BYTES 0x8f
59 #define CLK_WAIT_HIGH 0x94
60 #define CLK_WAIT_LOW 0x95
61 #define EN_ADAPTIVE 0x96
62 #define DIS_ADAPTIVE 0x97
63 #define CLK_BYTES_OR_HIGH 0x9c
64 #define CLK_BYTES_OR_LOW 0x0d
65 /*FT232H specific commands */
66 #define DRIVE_OPEN_COLLECTOR 0x9e
67 /* Value Low */
68 /* Value HIGH */ /*rate is 12000000/((1+value)*2) */
69 #define DIV_VALUE(rate) (rate > 6000000)?0:((6000000/rate -1) > 0xffff)? 0xffff: (6000000/rate -1)
70
71 /* Commands in MPSSE and Host Emulation Mode */
72 #define SEND_IMMEDIATE 0x87
73 #define WAIT_ON_HIGH 0x88
74 #define WAIT_ON_LOW 0x89
75
76 /* Commands in Host Emulation Mode */
77 #define READ_SHORT 0x90
78 /* Address_Low */
79 #define READ_EXTENDED 0x91
80 /* Address High */
81 /* Address Low */
82 #define WRITE_SHORT 0x92
83 /* Address_Low */
84 #define WRITE_EXTENDED 0x93
85 /* Address High */
86 /* Address Low */
87
88 /* Definitions for flow control */
89 #define SIO_RESET 0 /* Reset the port */
90 #define SIO_MODEM_CTRL 1 /* Set the modem control register */
91 #define SIO_SET_FLOW_CTRL 2 /* Set flow control register */
92 #define SIO_SET_BAUD_RATE 3 /* Set baud rate */
93 #define SIO_SET_DATA 4 /* Set the data characteristics of the port */
94
95 #define FTDI_DEVICE_OUT_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_OUT)
96 #define FTDI_DEVICE_IN_REQTYPE (USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_IN)
97
98 /* Requests */
99 #define SIO_RESET_REQUEST SIO_RESET
100 #define SIO_SET_BAUDRATE_REQUEST SIO_SET_BAUD_RATE
101 #define SIO_SET_DATA_REQUEST SIO_SET_DATA
102 #define SIO_SET_FLOW_CTRL_REQUEST SIO_SET_FLOW_CTRL
103 #define SIO_SET_MODEM_CTRL_REQUEST SIO_MODEM_CTRL
104 #define SIO_POLL_MODEM_STATUS_REQUEST 0x05
105 #define SIO_SET_EVENT_CHAR_REQUEST 0x06
106 #define SIO_SET_ERROR_CHAR_REQUEST 0x07
107 #define SIO_SET_LATENCY_TIMER_REQUEST 0x09
108 #define SIO_GET_LATENCY_TIMER_REQUEST 0x0A
109 #define SIO_SET_BITMODE_REQUEST 0x0B
110 #define SIO_READ_PINS_REQUEST 0x0C
111 #define SIO_READ_EEPROM_REQUEST 0x90
112 #define SIO_WRITE_EEPROM_REQUEST 0x91
113 #define SIO_ERASE_EEPROM_REQUEST 0x92
114
115 #define SIO_RESET_SIO 0
116 #define SIO_RESET_PURGE_RX 1
117 #define SIO_RESET_PURGE_TX 2
118
119 #define SIO_DISABLE_FLOW_CTRL 0x0
120 #define SIO_RTS_CTS_HS (0x1 << 8)
121 #define SIO_DTR_DSR_HS (0x2 << 8)
122 #define SIO_XON_XOFF_HS (0x4 << 8)
123
124 #define SIO_SET_DTR_MASK 0x1
125 #define SIO_SET_DTR_HIGH ( 1 | ( SIO_SET_DTR_MASK << 8))
126 #define SIO_SET_DTR_LOW ( 0 | ( SIO_SET_DTR_MASK << 8))
127 #define SIO_SET_RTS_MASK 0x2
128 #define SIO_SET_RTS_HIGH ( 2 | ( SIO_SET_RTS_MASK << 8 ))
129 #define SIO_SET_RTS_LOW ( 0 | ( SIO_SET_RTS_MASK << 8 ))
130
131 #define SIO_RTS_CTS_HS (0x1 << 8)