FreeCalypso > hg > freecalypso-citrine

annotate nucleus/demo/tmcal.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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75a11d740a02 initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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Mychaela Falconia <falcon@freecalypso.org>
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2 * FreeNucleus port by Spacefalcon the Outlaw
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Mychaela Falconia <falcon@freecalypso.org>
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3 *
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Mychaela Falconia <falcon@freecalypso.org>
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4 * This module implements the INT_Timer_Initialize() function
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Mychaela Falconia <falcon@freecalypso.org>
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5 * for the proof-of-concept Calypso port.
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Mychaela Falconia <falcon@freecalypso.org>
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6 *
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Mychaela Falconia <falcon@freecalypso.org>
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7 * TIMER2 configuration is based on that used by OsmocomBB.
75a11d740a02 initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
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8 */
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Mychaela Falconia <falcon@freecalypso.org>
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9
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Mychaela Falconia <falcon@freecalypso.org>
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10 #include "calirq.h"
75a11d740a02 initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
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11 #include "caltimer.h"
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Mychaela Falconia <falcon@freecalypso.org>
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12
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Mychaela Falconia <falcon@freecalypso.org>
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13 void
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Mychaela Falconia <falcon@freecalypso.org>
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14 INT_Timer_Initialize()
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Mychaela Falconia <falcon@freecalypso.org>
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15 {
75a11d740a02 initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
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16 /* program the timer */
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Mychaela Falconia <falcon@freecalypso.org>
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17 TIMER2_REGS.cntl = CNTL_CLOCK_ENABLE;
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Mychaela Falconia <falcon@freecalypso.org>
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18 TIMER2_REGS.load = 4062;
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Mychaela Falconia <falcon@freecalypso.org>
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19 TIMER2_REGS.cntl = CNTL_CLOCK_ENABLE | CNTL_AUTO_RELOAD | CNTL_START;
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Mychaela Falconia <falcon@freecalypso.org>
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20 /* now let it interrupt */
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Mychaela Falconia <falcon@freecalypso.org>
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21 INTH_REGS.ilr_irq[IRQ_TIMER2] = 0x7E;
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22 INTH_REGS.mask_it_reg1 &= ~(1 << IRQ_TIMER2);
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23 }