FreeCalypso > hg > freecalypso-hwlab
annotate doc/Calypso-OpenOCD-Howto @ 88:91486a77643e
fc-simtool: implement hex display of full SIM responses
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 24 Jan 2021 05:09:48 +0000 |
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1 Using OpenOCD to operate on Calypso JTAG: proof of concept |
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2 ========================================================== |
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3 |
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4 We have a proof-of-concept OpenOCD configuration for talking to Calypso JTAG |
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5 based on the theoretical findings described in the Calypso-JTAG-notes document |
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6 in the freecalypso-docs repository; the present document describes how one can |
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7 practically use OpenOCD on an FCDEV3B target. |
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8 |
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9 Choice of JTAG adapter hardware |
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10 =============================== |
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11 |
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12 The PoC presented here uses an off-the-shelf unbuffered FT2232D breakout board |
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13 with a special EEPROM configuration as the JTAG adapter, as described in the |
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14 Unbuffered-FT2232x-JTAG article. ADBUS0 through ADBUS3 are wired to standard |
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15 JTAG signals as required by FTDI and ADBUS7 (acting as a GPIO) is wired to the |
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16 XDS_RESET line on JTAG connector pin 2. This choice of using a generic FT2232D |
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17 breakout board as opposed to a more purpose-made "professional" JTAG adapter |
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18 was made deliberately in order to force the user to make a mental shift |
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19 regarding reset signals: any standard JTAG adapter product will have two reset |
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20 outputs designated as TRST and SRST, but the XDS_RESET signal on the FCDEV3B |
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21 does not correspond to either of those. But a generic (non-JTAG-specific) |
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22 FT2232x breakout board does not have TRST or SRST, it only has ADBUS and ACBUS |
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23 pins that become GPIOs in MPSSE mode, allowing the user to break out of the |
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24 TRST and SRST mentality: you just have a bunch of GPIOs, then arbitrarily pick |
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25 one of those GPIOs and connect it to XDS_RESET, *without* associating it with |
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26 either TRST or SRST. |
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27 |
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28 The full set of needed wire connections is thus: |
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29 |
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30 FT2232D signal FCDEV3B JTAG signal |
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31 ----------------------------------- |
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32 ADBUS0 TCK (pin 11) |
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33 ADBUS1 TDI (pin 3) |
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34 ADBUS2 TDO (pin 7) |
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35 ADBUS3 TMS (pin 1) |
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36 ADBUS7 XDS_RESET (pin 2) |
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37 |
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38 You will also need to connect at least one ground pin, hence 6 wires in total. |
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39 There is no need to connect the undocumented and non-understood EMU0 and EMU1 |
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40 signals - we don't know what to do with them and we work without them. This |
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41 wiring arrangement and all functionality described in this article work exactly |
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42 the same way on both D-Sample and FCDEV3B boards. You will also need to |
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43 reprogram the EEPROM on the FT2232D board as described in the |
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44 Unbuffered-FT2232x-JTAG article *before* you connect it to the Calypso target |
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45 board. |
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46 |
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47 One can also connect just the 4 JTAG wires, without reset: there are some |
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48 historical commercial phones and modems on which JTAG lines are accessible, but |
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49 Iota nTESTRESET is not, or perhaps nTESTRESET is accessible, but you don't feel |
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50 like replicating the transistor circuit that is required in order to drive it |
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51 safely - the circuit that is present on development boards, but not on hacked-up |
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52 phones and modems. In that case you will still be able to halt an already- |
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53 running Calypso, but of course you won't be able to exercise reset_halt or |
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54 reset_run operations described below. |
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55 |
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56 Unpowered FT2232D adapter quirk |
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57 =============================== |
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58 |
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59 If you connect the FT2232D board to the FCDEV3B as described above, including |
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60 the XDS_RESET signal and ground, you will notice the following quirk: if the |
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61 custom-crimped JTAG cable is connected between the two boards, but the FT2232D |
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62 board is not plugged into a USB host (has no USB power), the FCDEV3B will be |
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63 held down in test reset: the green LED will be off, and neither button on the |
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64 board will do anything. The FCDEV3B will be released from this reset and will |
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65 boot in test reset mode with the green LED on the moment you plug the FT2232D |
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66 board into your USB host. |
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67 |
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68 Running OpenOCD |
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69 =============== |
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70 |
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71 With the FT2232D board plugged into your host PC or laptop and programmed with |
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72 the custom USB ID of 0403:7151, you can run OpenOCD with the custom config file |
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73 presented in the calypso-jtag directory in this repository: |
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74 |
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75 openocd -f ft2232d-unbuf-poc.cfg |
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76 |
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77 Being a proof of concept, this OpenOCD config file does not follow any of the |
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78 guidelines regarding separation between adapters and targets, but is fully |
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79 monolithic instead. This config is written to work with openocd-0.10.0 |
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80 (depends on the new ftdi driver), but does NOT use the target/ti_calypso.cfg |
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81 fragment that has been included in mainline OpenOCD for quite some time: in the |
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82 Mother's opinion, the latter is bogus. If someone wishes to bring Calypso |
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83 support in the mainline OpenOCD distribution up to par, I do not have any |
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84 advice or guidance for you: it is your job, not mine. The present PoC config |
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85 that is rather antagonistic to mainline OpenOCD, its framework and its |
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86 guidelines will always remain our standard answer to FreeCalypso customers |
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87 asking how to make JTAG work. |
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88 |
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89 When you run OpenOCD as above, the FCDEV3B target needs to be in the running |
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90 state with the green LED on. OpenOCD will exercise and verify the scan chain, |
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91 but it won't issue any resets or halts on its own, thus whatever code was |
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92 running on the board won't be disturbed in any way by the act of running |
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93 OpenOCD. You can then reset and/or halt the target as desired with our custom |
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94 commands (Tcl procedures) as described below. |
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95 |
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96 Halting the Calypso without a reset |
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97 =================================== |
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98 |
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99 To halt an already-running Calypso ARM7 core without a reset, stopping it at |
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100 whatever point it happens to be in its code execution, execute this sequence: |
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101 |
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102 enable_halt; halt |
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103 |
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104 The enable_halt step is a custom Tcl procedure added by us, issuing the |
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105 mysterious 0xB instruction and DR scan that are needed in order to enable halts |
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106 on TI's modified version of the ARM7TDMI core. Once you have halted as above, |
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107 you can resume and halt again without needing to re-execute the enable_halt |
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108 step; the only time when the enable_halt step will need to be repeated is when |
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109 the Calypso is reset. |
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110 |
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111 You can safely halt the Calypso in this manner when the flash is blank and the |
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112 boot ROM waits forever for a serial download, when you have loaded a RAM image |
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113 with fc-xram -j and the target is left in loadagent, or when one of our standard |
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114 firmwares is running; in all of these states the Calypso watchdog timer is |
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115 disabled. However, if you are going to halt the Calypso when the watchdog timer |
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116 is running, you will need to execute our wd (watchdog disable) command quickly |
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117 after the halt, before the watchdog timer is allowed to expire. A simple way |
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118 would be: |
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119 |
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120 enable_halt; halt; wd |
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121 |
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122 The wd command (Tcl procedure) name was deliberately made short so it can be |
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123 typed quickly with fingers if need be. |
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124 |
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125 Resetting with or without a halt |
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126 ================================ |
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127 |
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128 We don't support OpenOCD's standard reset command because we found it too |
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129 difficult to override its built-in assumptions which are wrong for our Calypso. |
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130 Instead we have our own reset_halt and reset_run custom commands (Tcl |
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131 procedures) that replace OpenOCD's standard 'reset halt' and 'reset run', |
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132 respectively. |
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133 |
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134 The reset_run command will reset the board without halting the Calypso, letting |
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135 it boot and run normally. It is equivalent to pressing the RESET button on the |
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136 board with your finger, except that it also re-initializes OpenOCD's scan scain |
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137 and "target examination" state which would otherwise get confused. |
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138 |
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139 The reset_halt command will reset the board and halt the Calypso immediately as |
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140 it comes out of reset, halting at the reset vector before the first instruction |
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141 of the boot ROM code (or the first instruction from external memory if operating |
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142 on a D-Sample board with the boot switch set to external) is executed. The |
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143 necessary disabling of the watchdog timer (wd procedure call) is already built |
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144 into the reset_halt Tcl procedure; except for this wd step, all Calypso and Iota |
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145 registers will be in their most pristine reset state. |
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146 |
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147 Recovering bricked Compal phones |
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148 ================================ |
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149 |
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150 Some Mot C1xx phones have Calypso JTAG signals brought out to accessible contact |
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151 pads, allowing a way to recover from a bricked flash bootloader via JTAG. |
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152 However, they do not bring out Iota nTESTRESET, instead they bring out a signal |
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153 which they call DLPWR, which is really Iota RPWON. A procedure similar to our |
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154 reset_halt would need to be performed as the first step in the recovery |
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155 sequence, but it would need to be modified to work with DLPWR instead of |
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156 XDS_RESET. The RPWON aka DLPWR signal will need to be driven with an OC/OD |
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157 driver (it is internally pulled up to raw VBAT, which is not a safe voltage for |
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158 standard 3.3V logic), and the switch-on and boot sequence will be triggered |
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159 when this signal is pulled low, i.e., transitions from high to low. The |
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160 subsequent release transition (from low back to pull-up high) does not matter, |
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161 i.e., RPWON may be permanently pulled down as the Calypso boots and runs, very |
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162 much unlike nTESTRESET or XDS_RESET. |
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163 |
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164 It will be up to you to design whatever circuit you wish to use to produce an |
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165 OC/OD driver that can be triggered from OpenOCD, but connecting RPWON aka DLPWR |
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166 directly to an FT2232x I/O pin is not acceptable. Copying the circuit from |
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167 TI/FC development boards that propagates XDS_RESET into nTESTRESET won't work |
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168 either: this circuit only works when the V-IO regulator is already on, but |
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169 RPWON is not a reset and will need to be triggered when the chipset is fully |
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170 "cold". |
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171 |
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172 You will also need to figure out the appropriate timing. You will need to |
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173 insert a certain delay between RPWON assertion and the 'jtag arp_init' step in |
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174 our reset_halt procedure: the VRPC state machine in the Iota chip will do a |
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175 bunch of work between sensing a low on RPWON and releasing the Calypso from |
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176 reset via ON_nOFF, and until then the JTAG scan chain won't work. But the |
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177 delay cannot be too long either, or you won't halt the Calypso before it starts |
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178 executing bogus code from the phone's bricked flash. |
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179 |
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180 Once you do get a working reset_halt variant, the following steps will be |
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181 straightforward: |
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182 |
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183 1) Run fc-loadtool -h compal -c none /dev/ttyXXX on the serial port connected |
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184 to the phone's headset jack; |
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185 |
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186 2) Enable the boot ROM and jump to it with these commands: |
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187 |
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188 mwh 0xFFFFFB10 0x100 |
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189 resume 0 |
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190 |
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191 The boot ROM will run while fc-loadtool is sending its beacons, fc-loadtool |
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192 will load and run loadagent, and you can then recover the flash. |
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193 |
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194 Lack of performance optimizations |
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195 ================================= |
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196 |
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197 Our PoC OpenOCD-on-Calypso config does not set up a work area (an area of |
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198 system RAM that is declared as a scratchpad for OpenOCD), nor does it enable |
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199 arm7_9 dcc_downloads or arm7_9 fast_memory_access. These omissions are |
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200 intentional, as those performance optimizations are outside of the scope of |
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201 what I set out to do, which is to prove Calypso JTAG as working and provide a |
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202 "golden reference" setup. |
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203 |
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204 If you wish to set up an area in Calypso IRAM as a work area for OpenOCD, which |
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205 is a prerequisite for arm7_9 dcc_downloads, you will need to choose the location |
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206 based on your specific application - whether a given area will be suitable or |
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207 not will depend on exactly what you are debugging and exactly what you are |
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208 trying to do, which is once again outside of the scope of this PoC. |