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comparison doc/Calypso-OpenOCD-Howto @ 64:6d02f30e35ad

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doc/Calypso-OpenOCD-Howto: noted lack of performance optimizations
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 29 Jun 2019 22:45:18 +0000
parents 66879ce73b3e
children
comparison
equal deleted inserted replaced
63:66879ce73b3e 64:6d02f30e35ad
103 103
104 The enable_halt step is a custom Tcl procedure added by us, issuing the 104 The enable_halt step is a custom Tcl procedure added by us, issuing the
105 mysterious 0xB instruction and DR scan that are needed in order to enable halts 105 mysterious 0xB instruction and DR scan that are needed in order to enable halts
106 on TI's modified version of the ARM7TDMI core. Once you have halted as above, 106 on TI's modified version of the ARM7TDMI core. Once you have halted as above,
107 you can resume and halt again without needing to re-execute the enable_halt 107 you can resume and halt again without needing to re-execute the enable_halt
108 step; the only time when the enable_halt steps will need to be repeated is when 108 step; the only time when the enable_halt step will need to be repeated is when
109 the Calypso is reset. 109 the Calypso is reset.
110 110
111 You can safely halt the Calypso in this manner when the flash is blank and the 111 You can safely halt the Calypso in this manner when the flash is blank and the
112 boot ROM waits forever for a serial download, when you have loaded a RAM image 112 boot ROM waits forever for a serial download, when you have loaded a RAM image
113 with fc-xram -j and the target is left in loadagent, or when one of our standard 113 with fc-xram -j and the target is left in loadagent, or when one of our standard
162 much unlike nTESTRESET or XDS_RESET. 162 much unlike nTESTRESET or XDS_RESET.
163 163
164 It will be up to you to design whatever circuit you wish to use to produce an 164 It will be up to you to design whatever circuit you wish to use to produce an
165 OC/OD driver that can be triggered from OpenOCD, but connecting RPWON aka DLPWR 165 OC/OD driver that can be triggered from OpenOCD, but connecting RPWON aka DLPWR
166 directly to an FT2232x I/O pin is not acceptable. Copying the circuit from 166 directly to an FT2232x I/O pin is not acceptable. Copying the circuit from
167 TI/FC development boards that propagates XDS_RESET into nTESTRESET won't work: 167 TI/FC development boards that propagates XDS_RESET into nTESTRESET won't work
168 this circuit only works when the V-IO regulator is already on, but RPWON is not 168 either: this circuit only works when the V-IO regulator is already on, but
169 a reset and will need to be triggered when the chipset is fully "cold". 169 RPWON is not a reset and will need to be triggered when the chipset is fully
170 "cold".
170 171
171 You will also need to figure out the appropriate timing. You will need to 172 You will also need to figure out the appropriate timing. You will need to
172 insert a certain delay between RPWON assertion and the 'jtag arp_init' step in 173 insert a certain delay between RPWON assertion and the 'jtag arp_init' step in
173 our reset_halt procedure: the VRPC state machine in the Iota chip will do a 174 our reset_halt procedure: the VRPC state machine in the Iota chip will do a
174 bunch of work between sensing a low on RPWON and releasing the Calypso from 175 bunch of work between sensing a low on RPWON and releasing the Calypso from
187 mwh 0xFFFFFB10 0x100 188 mwh 0xFFFFFB10 0x100
188 resume 0 189 resume 0
189 190
190 The boot ROM will run while fc-loadtool is sending its beacons, fc-loadtool 191 The boot ROM will run while fc-loadtool is sending its beacons, fc-loadtool
191 will load and run loadagent, and you can then recover the flash. 192 will load and run loadagent, and you can then recover the flash.
193
194 Lack of performance optimizations
195 =================================
196
197 Our PoC OpenOCD-on-Calypso config does not set up a work area (an area of
198 system RAM that is declared as a scratchpad for OpenOCD), nor does it enable
199 arm7_9 dcc_downloads or arm7_9 fast_memory_access. These omissions are
200 intentional, as those performance optimizations are outside of the scope of
201 what I set out to do, which is to prove Calypso JTAG as working and provide a
202 "golden reference" setup.
203
204 If you wish to set up an area in Calypso IRAM as a work area for OpenOCD, which
205 is a prerequisite for arm7_9 dcc_downloads, you will need to choose the location
206 based on your specific application - whether a given area will be suitable or
207 not will depend on exactly what you are debugging and exactly what you are
208 trying to do, which is once again outside of the scope of this PoC.