FreeCalypso > hg > freecalypso-reveng
annotate bootrom.notes @ 282:52d21957bf2e
compal/sym-fw-disasm: initial analysis
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 14 Mar 2019 06:55:02 +0000 |
parents | cf3b4cb3d212 |
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rev | line source |
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1 Application images in flash: |
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2 |
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3 In order for the nCS0 flash content to be considered a valid bootable image |
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4 (i.e., for the boot ROM to transfer control to it, rather than wait forever |
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5 for a UART download), the 32-bit word at address 0x2000 (the first word |
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6 after the ROM-overlaid portion) must contain either 0 or 1, corresponding |
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7 to two supported environment options: |
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8 |
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9 * If the word at 0x2000 equals 0, it signifies an application image that is |
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10 designed to run with the boot ROM still mapped at 0, with ARM exceptions |
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11 vectoring through the 7 magic RAM locations at 0x80001C, and possibly |
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12 through the 2nd level ("user-friendly") vector table at 0x800000 as well. |
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13 |
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14 If the word at 0x2000 equals 0, the following word at 0x2004 must contain |
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15 the absolute address of the boot entry point; the boot ROM will transfer |
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16 control to that address with the FFFF:FB10 register set to explicitly map |
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17 the internal boot ROM at 0. It is a BX-style address: setting the least |
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18 significant bit will result in control being transferred in the Thumb state. |
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19 |
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20 * If the word at 0x2000 equals 1, it signifies an application image that is |
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21 at least conceptually independent of the Calypso boot ROM - one that would, |
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22 at least in theory, function correctly with nIBOOT tied/pulled/driven HIGH, |
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23 or even on an older DBB chip with no internal boot ROM. |
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24 |
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25 When the boot ROM code sees a 1 in the 0x2000 word, it copies a little piece |
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cf3b4cb3d212
bootrom.notes typo fix (courtesy of pfalcon <pmiscml@gmail.com>)
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26 of code into the internal RAM and runs it there; this code sets the FFFF:FB10 |
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27 register to disable the internal boot ROM (map the external nCS0 memory at 0, |
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28 as if nIBOOT were high) and causes the watchdog timer to go off, resetting |
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29 the ARM core and causing it to execute the external nCS0 reset vector. |
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30 |
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31 UART protocol |
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32 |
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33 The external host initiates every operation by sending a command to the |
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34 Calypso target running the boot ROM code. Every command begins with '<' and |
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35 a lowercase ASCII letter; just the initial '<' is sufficient to interrupt |
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36 the flash image autoboot. The external host shound send these commands at |
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37 19200 baud, 8N1, and the boot ROM will intuit whether the Calypso is being |
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38 clocked with 13 or 26 MHz by trying the two possible clocking setups |
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39 alternately, with the UART baud rate registers set to /42 in both cases, |
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40 until a clean '<' is received. |
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41 |
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42 Once the initial '<' has been received on either UART, the boot ROM only |
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43 listens on that port from there onward. There is a timeout between the |
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44 successive bytes of a single command, but the ROM will wait forever |
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45 for another '<'. |
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46 |
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47 Commands: |
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48 |
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49 <a |
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50 |
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51 Seems to be a reset command that throws everything back to the initial state. |
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52 Does not seem to produce a response. |
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53 |
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54 <b |
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55 |
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56 Branch command. |
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57 |
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58 Followed by 4 bytes, giving the 32-bit branch address in MSB-first order. |
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59 It is a BX-style address, i.e., setting the least significant bit will |
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60 cause the code to be jumped to in the Thumb state. |
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61 |
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62 The address is written to 80052C, and the 0x2c8 function returns code 6. |
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63 |
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64 If the command is accepted, a '>b' response is sent back before the |
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65 jump is performed. If the command is rejected because the downloader |
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66 is in the wrong state (see below), a '>B' response is sent back, and |
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67 the downloader is reset to its initial state, waiting for commands at |
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68 19200 baud. |
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69 |
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70 <c |
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71 |
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72 Checksum verification command. The <c characters need to be followed by a |
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73 single binary byte, which need to equal the one's complement of the low byte |
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74 of the 800528 accumulator. |
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75 |
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76 Response: >c if good, >C if bad. Both are followed by the low byte of 800528. |
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77 |
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78 <i |
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79 |
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80 Calls the 0x11c routine, then responds with '>i'. |
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81 |
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82 <p |
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83 |
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84 Set parameters |
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85 |
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86 Followed by 9 bytes: |
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87 1 byte: goes into var at 800518, selects the baud rate: |
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88 0: 115200 |
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89 1: 57600 |
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90 2: 38400 |
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91 3: 28800 |
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92 4: 19200 |
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93 1 byte: goes into var at 800521, controls the 0xef4 routine: |
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94 bits <6:2>: R2 arg (PLL_MULT field) |
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95 bits <1:0>: R1 arg (PLL_DIV field) |
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96 2 bytes: 16-bit MSB-first value goes into var at 800522 |
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97 word gives arguments to 0xe2c routine, breaks down as follows: |
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98 bit 15: unused |
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99 <14:10> arg3 |
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100 <9:5> arg2 |
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101 <4:0> arg1 |
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102 1 byte: goes into var at 800525 |
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103 remaining arguments to 0xe2c: |
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104 <7:4> arg5 |
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105 <3:0> arg4 |
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106 4 bytes: 32-bit MSG-first value goes into var at 80051C |
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107 reloads the UART timeout variable 800104 |
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108 |
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109 Good response: >p 00 04 (4 bytes total) |
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110 The baud rate is switched after the above response is sent. |
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111 |
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112 Error response: >P |
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113 |
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114 <w |
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115 |
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116 Write data to RAM |
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117 |
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118 Followed by: |
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119 1 byte: block number (of this block) |
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120 1 byte: total # of blocks |
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121 2 bytes: # of payload bytes in this block (MSB first) |
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122 4 bytes: load address for this block (MSB first) |
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123 data |
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124 |
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125 For a single block (both bytes after <w set to 01), the maximum allowed |
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126 payload length is 1015 (0x3F7) bytes. |
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127 |
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128 No alignment required on the address or length - the copying from the |
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129 intermediate buffer at 80010C to the specified load address is done |
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130 with a loop that does one byte at a time with ldrb and strb instructions. |
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131 |
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132 The checksum of each block is computed as a simple ripple-carry sum |
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133 (in a 32-bit ARM register) of: |
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134 + the word-sized payload byte count from the command |
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135 + each of the 4 bytes of the load address |
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136 + constant 5 |
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137 + each byte of the payload data |
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138 |
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139 The code then takes a one's complement of the least significant byte |
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140 of the above sum, and adds that (plain ripple-carry addition) |
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141 to the accum in 800528 (a 16-bit variable). |
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142 |
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143 Good response: >w |
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144 Error response: >W <err code byte from 800531> |
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145 |
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146 UART download procedure |
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147 |
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148 Step 1: the external host sends a continuous stream of '<i' beacons at 19200 |
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149 baud, waiting for a '>i' response at the same baud rate. These beacons need |
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150 to be pouring down the wire into the Calypso UART while waiting for the user |
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151 to induce the Calypso target into executing the boot ROM (via battery |
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152 manipulations or other target-specific tricks). |
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153 |
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154 Step 2: when a '>i' response has been received, send a '<p' command with the |
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155 desired parameters. Expect a '>p' 00 04 response, still at the original |
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156 baud rate of 19200; if this response isn't received, it's an error. |
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157 |
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158 Step 2a: if the '<p' command specified a switch to a higher baud rate (up to |
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159 115200), have the external host switch its serial port configuration at this |
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160 point, after getting the >p response but before sending the next command. |
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161 |
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162 Step 3: send a series of '<w' commands, loading code into IRAM. (Only the |
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163 internal Calypso RAM may be loaded, not board level RAM.) Maintain a |
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164 running checksum like the boot ROM does. |
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165 |
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166 Step 4: send a '<c' command with the proper checksum value. A positive |
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167 response must be received before one can proceed to the branch. |
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168 |
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169 Step 5: send a '<b' command to transfer control to the just-loaded code. |
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170 |
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171 The implementation of this protocol on the boot ROM side contains a state |
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172 machine which enforces the above order: |
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173 |
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174 * a '<p' command is required before '<w' will be accepted |
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175 * after that '<p', one or more '<w's and a '<c' with the correct checksum |
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176 value must be received in order to enable the '<b' command. |
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177 |
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178 Errors result in the state machine being reset to the initial state; |
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179 the baud rate at which the boot ROM expects to receive commands reverts |
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180 to the initial 19200. |
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181 |
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182 RAM layout: |
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183 |
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184 800000 7 words: |
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185 soft-vector pointers: by default the following 7 words at |
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186 80001C are filled with ldr-jump instructions, which read |
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187 from these 7 words and load them into PC |
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188 80001C 7 words: |
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189 hard vectors: the physical vector locations in the ROM |
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190 contain branch instructions to these 7 RAM addresses |
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191 800038: The helper routine for transferring control to type 1 flash images |
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192 is copied to and run here. |
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193 800100: the last word of the above routine |
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194 800104: word initialized to 0x0001D4C0 - tells the 0x2c8 routine |
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195 how long to wait for a character |
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196 800108: byte initialized to 0x01 |
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197 state variable for the serial command interface |
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198 in the initial state of 01, only <i and <p are accepted |
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199 state 02: after successful <p, <w is allowed |
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200 state 03: after first successful <w, and subsequent successful <w's |
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201 state 04: after <c with matching checksum |
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202 80010C: all bytes of a '<w' command after these two command chars |
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203 are stored starting here |
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204 this buffer is also used for other scratchpad functions: <p |
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205 command bytes, all response messages |
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206 80050B: the above buffer ends here |
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207 |
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208 The group of vars starting at 800518 may have been envisioned |
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209 as a struct - see the routine at 0x11c: |
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210 |
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211 800518: byte variable receives the first parameter byte after '<p' |
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212 baud rate code ([0,4] range) |
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213 init to 04 by '<i' |
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214 80051C: 32-bit var set by the '<p' command |
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215 reloads the UART timeout variable 800104 |
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216 800520: byte variable filled every time the 0xfb4 routine is called |
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217 holds the ID of the UART on which '<' came in, or FF if none |
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218 800521: byte variable receives the 2nd parameter byte after '<p' |
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219 PLL config |
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boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
12
diff
changeset
|
220 800522: 16-bit var set by the '<p' command |
16
383a4ef12551
boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
14
diff
changeset
|
221 chip select wait state config |
8
a06573cacb6e
boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
7
diff
changeset
|
222 800524: byte variable filled every time the 0xfb4 routine is called |
a06573cacb6e
boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
7
diff
changeset
|
223 filled with a copy of 800534 |
13
e0ce45f043c0
boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
12
diff
changeset
|
224 800525: byte var set by the '<p' command |
16
383a4ef12551
boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
14
diff
changeset
|
225 config for the FFFF:F900 register (0xe2c routine) |
14
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
226 800526: 16-bit var init to 0 by 0x11c ('<i' handler) |
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
227 byte following the '<c' command is extended to a half-word and |
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
228 written here |
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
229 800528: 16-bit var init to 0 by 0x11c ('<i' handler) |
16
383a4ef12551
boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
14
diff
changeset
|
230 checksum accum? |
8
a06573cacb6e
boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
7
diff
changeset
|
231 |
14
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
232 80052C: 32-bit var init to 0 by 0x11c ('<i' handler) |
18
123cb5021b64
boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
17
diff
changeset
|
233 word holds the argument of the '<b' command, i.e., the branch address |
14
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
234 800530: byte indicates validity of the received '<w' command: |
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
235 0 means valid, 1 means something bad |
3443b1b08af4
boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
13
diff
changeset
|
236 init to 0 by 0x11c |
17
d2206cb5f8b4
boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
16
diff
changeset
|
237 800531: byte error code to return to host as the 3rd (and last) byte |
d2206cb5f8b4
boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
16
diff
changeset
|
238 of the >W message |
d2206cb5f8b4
boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
16
diff
changeset
|
239 set to 02 if the 800530 flag was set |
d2206cb5f8b4
boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
16
diff
changeset
|
240 set to 01 if the 0x730 routine detects bad address |
12
25b016d16602
boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
8
diff
changeset
|
241 |
8
a06573cacb6e
boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
7
diff
changeset
|
242 800534: byte initialized to 0x00, then may be set to 1 by the 0xfb4 |
a06573cacb6e
boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
7
diff
changeset
|
243 routine if it selects /1 clock mode. |
3
e3f8fe6a848e
boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
244 |
e3f8fe6a848e
boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
245 8005C0: appears to be the intended low address (bottom) of the stack |
e3f8fe6a848e
boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
246 80074C: top of the stack (initial value loaded into SP) |
13
e0ce45f043c0
boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
12
diff
changeset
|
247 800750: lowest address at which user code may be loaded |