FreeCalypso > hg > freecalypso-reveng

annotate bootrom.notes @ 245:9cd7fa86da47

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pirelli/fw-disasm: l1_initialize() located
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 23 Dec 2017 23:26:06 +0000
parents cf3b4cb3d212
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
7
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
1 Application images in flash:
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
2
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
3 In order for the nCS0 flash content to be considered a valid bootable image
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
4 (i.e., for the boot ROM to transfer control to it, rather than wait forever
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
5 for a UART download), the 32-bit word at address 0x2000 (the first word
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
6 after the ROM-overlaid portion) must contain either 0 or 1, corresponding
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
7 to two supported environment options:
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
8
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
9 * If the word at 0x2000 equals 0, it signifies an application image that is
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
10 designed to run with the boot ROM still mapped at 0, with ARM exceptions
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
11 vectoring through the 7 magic RAM locations at 0x80001C, and possibly
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
12 through the 2nd level ("user-friendly") vector table at 0x800000 as well.
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
13
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
14 If the word at 0x2000 equals 0, the following word at 0x2004 must contain
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
15 the absolute address of the boot entry point; the boot ROM will transfer
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
16 control to that address with the FFFF:FB10 register set to explicitly map
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
17 the internal boot ROM at 0. It is a BX-style address: setting the least
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
18 significant bit will result in control being transferred in the Thumb state.
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
19
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
20 * If the word at 0x2000 equals 1, it signifies an application image that is
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
21 at least conceptually independent of the Calypso boot ROM - one that would,
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
22 at least in theory, function correctly with nIBOOT tied/pulled/driven HIGH,
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
23 or even on an older DBB chip with no internal boot ROM.
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
24
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
25 When the boot ROM code sees a 1 in the 0x2000 word, it copies a little piece
197
cf3b4cb3d212 bootrom.notes typo fix (courtesy of pfalcon <pmiscml@gmail.com>)
Michael Spacefalcon <falcon@ivan.Harhan.ORG>
parents: 20
diff changeset
26 of code into the internal RAM and runs it there; this code sets the FFFF:FB10
7
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
27 register to disable the internal boot ROM (map the external nCS0 memory at 0,
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
28 as if nIBOOT were high) and causes the watchdog timer to go off, resetting
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
29 the ARM core and causing it to execute the external nCS0 reset vector.
a445735685ba boot ROM re: flash application image interface documented
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 3
diff changeset
30
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
31 UART protocol
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
32
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
33 The external host initiates every operation by sending a command to the
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
34 Calypso target running the boot ROM code. Every command begins with '<' and
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
35 a lowercase ASCII letter; just the initial '<' is sufficient to interrupt
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
36 the flash image autoboot. The external host shound send these commands at
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
37 19200 baud, 8N1, and the boot ROM will intuit whether the Calypso is being
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
38 clocked with 13 or 26 MHz by trying the two possible clocking setups
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
39 alternately, with the UART baud rate registers set to /42 in both cases,
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
40 until a clean '<' is received.
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
41
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
42 Once the initial '<' has been received on either UART, the boot ROM only
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
43 listens on that port from there onward. There is a timeout between the
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
44 successive bytes of a single command, but the ROM will wait forever
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
45 for another '<'.
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
46
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
47 Commands:
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
48
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
49 <a
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
50
17
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
51 Seems to be a reset command that throws everything back to the initial state.
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
52 Does not seem to produce a response.
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
53
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
54 <b
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
55
20
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
56 Branch command.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
57
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
58 Followed by 4 bytes, giving the 32-bit branch address in MSB-first order.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
59 It is a BX-style address, i.e., setting the least significant bit will
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
60 cause the code to be jumped to in the Thumb state.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
61
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
62 The address is written to 80052C, and the 0x2c8 function returns code 6.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
63
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
64 If the command is accepted, a '>b' response is sent back before the
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
65 jump is performed. If the command is rejected because the downloader
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
66 is in the wrong state (see below), a '>B' response is sent back, and
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
67 the downloader is reset to its initial state, waiting for commands at
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
68 19200 baud.
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
69
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
70 <c
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
71
18
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
72 Checksum verification command. The <c characters need to be followed by a
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
73 single binary byte, which need to equal the one's complement of the low byte
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
74 of the 800528 accumulator.
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
75
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
76 Response: >c if good, >C if bad. Both are followed by the low byte of 800528.
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
77
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
78 <i
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
79
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
80 Calls the 0x11c routine, then responds with '>i'.
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
81
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
82 <p
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
83
20
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
84 Set parameters
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
85
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
86 Followed by 9 bytes:
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
87 1 byte: goes into var at 800518, selects the baud rate:
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
88 0: 115200
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
89 1: 57600
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
90 2: 38400
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
91 3: 28800
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
92 4: 19200
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
93 1 byte: goes into var at 800521, controls the 0xef4 routine:
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
94 bits <6:2>: R2 arg (PLL_MULT field)
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
95 bits <1:0>: R1 arg (PLL_DIV field)
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
96 2 bytes: 16-bit MSB-first value goes into var at 800522
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
97 word gives arguments to 0xe2c routine, breaks down as follows:
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
98 bit 15: unused
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
99 <14:10> arg3
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
100 <9:5> arg2
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
101 <4:0> arg1
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
102 1 byte: goes into var at 800525
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
103 remaining arguments to 0xe2c:
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
104 <7:4> arg5
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
105 <3:0> arg4
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
106 4 bytes: 32-bit MSG-first value goes into var at 80051C
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
107 reloads the UART timeout variable 800104
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
108
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
109 Good response: >p 00 04 (4 bytes total)
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
110 The baud rate is switched after the above response is sent.
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
111
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
112 Error response: >P
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
113
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
114 <w
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
115
20
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
116 Write data to RAM
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
117
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
118 Followed by:
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
119 1 byte: block number (of this block)
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
120 1 byte: total # of blocks
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
121 2 bytes: # of payload bytes in this block (MSB first)
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
122 4 bytes: load address for this block (MSB first)
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
123 data
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
124
18
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
125 For a single block (both bytes after <w set to 01), the maximum allowed
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
126 payload length is 1015 (0x3F7) bytes.
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
127
18
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
128 No alignment required on the address or length - the copying from the
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
129 intermediate buffer at 80010C to the specified load address is done
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
130 with a loop that does one byte at a time with ldrb and strb instructions.
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
131
17
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
132 The checksum of each block is computed as a simple ripple-carry sum
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
133 (in a 32-bit ARM register) of:
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
134 + the word-sized payload byte count from the command
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
135 + each of the 4 bytes of the load address
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
136 + constant 5
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
137 + each byte of the payload data
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
138
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
139 The code then takes a one's complement of the least significant byte
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
140 of the above sum, and adds that (plain ripple-carry addition)
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
141 to the accum in 800528 (a 16-bit variable).
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
142
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
143 Good response: >w
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
144 Error response: >W <err code byte from 800531>
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
145
20
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
146 UART download procedure
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
147
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
148 Step 1: the external host sends a continuous stream of '<i' beacons at 19200
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
149 baud, waiting for a '>i' response at the same baud rate. These beacons need
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
150 to be pouring down the wire into the Calypso UART while waiting for the user
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
151 to induce the Calypso target into executing the boot ROM (via battery
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
152 manipulations or other target-specific tricks).
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
153
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
154 Step 2: when a '>i' response has been received, send a '<p' command with the
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
155 desired parameters. Expect a '>p' 00 04 response, still at the original
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
156 baud rate of 19200; if this response isn't received, it's an error.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
157
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
158 Step 2a: if the '<p' command specified a switch to a higher baud rate (up to
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
159 115200), have the external host switch its serial port configuration at this
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
160 point, after getting the >p response but before sending the next command.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
161
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
162 Step 3: send a series of '<w' commands, loading code into IRAM. (Only the
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
163 internal Calypso RAM may be loaded, not board level RAM.) Maintain a
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
164 running checksum like the boot ROM does.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
165
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
166 Step 4: send a '<c' command with the proper checksum value. A positive
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
167 response must be received before one can proceed to the branch.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
168
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
169 Step 5: send a '<b' command to transfer control to the just-loaded code.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
170
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
171 The implementation of this protocol on the boot ROM side contains a state
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
172 machine which enforces the above order:
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
173
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
174 * a '<p' command is required before '<w' will be accepted
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
175 * after that '<p', one or more '<w's and a '<c' with the correct checksum
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
176 value must be received in order to enable the '<b' command.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
177
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
178 Errors result in the state machine being reset to the initial state;
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
179 the baud rate at which the boot ROM expects to receive commands reverts
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
180 to the initial 19200.
a52e76c12e6b boot ROM re: some sensible documentation written up
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
diff changeset
181
3
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
182 RAM layout:
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
183
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
184 800000 7 words:
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
185 soft-vector pointers: by default the following 7 words at
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
186 80001C are filled with ldr-jump instructions, which read
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
187 from these 7 words and load them into PC
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
188 80001C 7 words:
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
189 hard vectors: the physical vector locations in the ROM
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
190 contain branch instructions to these 7 RAM addresses
8
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
191 800038: The helper routine for transferring control to type 1 flash images
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
192 is copied to and run here.
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
193 800100: the last word of the above routine
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
194 800104: word initialized to 0x0001D4C0 - tells the 0x2c8 routine
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
195 how long to wait for a character
3
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
196 800108: byte initialized to 0x01
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
197 state variable for the serial command interface
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
198 in the initial state of 01, only <i and <p are accepted
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
199 state 02: after successful <p, <w is allowed
18
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
200 state 03: after first successful <w, and subsequent successful <w's
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
201 state 04: after <c with matching checksum
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
202 80010C: all bytes of a '<w' command after these two command chars
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
203 are stored starting here
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
204 this buffer is also used for other scratchpad functions: <p
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
205 command bytes, all response messages
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
206 80050B: the above buffer ends here
3
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
207
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
208 The group of vars starting at 800518 may have been envisioned
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
209 as a struct - see the routine at 0x11c:
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
210
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
211 800518: byte variable receives the first parameter byte after '<p'
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
212 baud rate code ([0,4] range)
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
213 init to 04 by '<i'
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
214 80051C: 32-bit var set by the '<p' command
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
215 reloads the UART timeout variable 800104
8
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
216 800520: byte variable filled every time the 0xfb4 routine is called
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
217 holds the ID of the UART on which '<' came in, or FF if none
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
218 800521: byte variable receives the 2nd parameter byte after '<p'
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
219 PLL config
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
220 800522: 16-bit var set by the '<p' command
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
221 chip select wait state config
8
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
222 800524: byte variable filled every time the 0xfb4 routine is called
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
223 filled with a copy of 800534
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
224 800525: byte var set by the '<p' command
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
225 config for the FFFF:F900 register (0xe2c routine)
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
226 800526: 16-bit var init to 0 by 0x11c ('<i' handler)
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
227 byte following the '<c' command is extended to a half-word and
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
228 written here
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
229 800528: 16-bit var init to 0 by 0x11c ('<i' handler)
16
383a4ef12551 boot ROM re: getting the download state machine, <p parsed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 14
diff changeset
230 checksum accum?
8
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
231
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
232 80052C: 32-bit var init to 0 by 0x11c ('<i' handler)
18
123cb5021b64 boot ROM re: appears to be complete!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 17
diff changeset
233 word holds the argument of the '<b' command, i.e., the branch address
14
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
234 800530: byte indicates validity of the received '<w' command:
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
235 0 means valid, 1 means something bad
3443b1b08af4 boot ROM re: starting to unravel the serial command handling
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 13
diff changeset
236 init to 0 by 0x11c
17
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
237 800531: byte error code to return to host as the 3rd (and last) byte
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
238 of the >W message
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
239 set to 02 if the 800530 flag was set
d2206cb5f8b4 boot ROM re: got through the <w handler
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 16
diff changeset
240 set to 01 if the 0x730 routine detects bad address
12
25b016d16602 boot ROM re: making inroads into the 0x2c8 routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 8
diff changeset
241
8
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
242 800534: byte initialized to 0x00, then may be set to 1 by the 0xfb4
a06573cacb6e boot ROM re: trying to understand the code that runs after '<' received
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 7
diff changeset
243 routine if it selects /1 clock mode.
3
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
244
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
245 8005C0: appears to be the intended low address (bottom) of the stack
e3f8fe6a848e boot ROM re: started on main() and the 0xe2c routine
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
246 80074C: top of the stack (initial value loaded into SP)
13
e0ce45f043c0 boot ROM re: continuing plowing through the serial protocol code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 12
diff changeset
247 800750: lowest address at which user code may be loaded