FreeCalypso > hg > freecalypso-reveng

annotate gtm900/interface-signals @ 365:f888ae294b1b

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fluid-mnf/README: should be complete now
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Mar 2020 08:59:12 +0000
parents c06cac606af3
children
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c06cac606af3 gtm900/interface-signals: notes from connection tracing
Mychaela Falconia <falcon@freecalypso.org>
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1 UART interfaces
c06cac606af3 gtm900/interface-signals: notes from connection tracing
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2 ===============
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3
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4 Both Calypso UARTs are brought out on the GTM900 module interface as follows:
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5
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6 Pin Name in manual Connected Calypso ball
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7 11 RXD2 TX_IRDA
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8 12 TXD2 RX_IRDA
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9 -------------------------------
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10 16 UART_DSR GPIO1
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11 17 UART_RI GPIO0
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12 18 UART_RXD TX_MODEM
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13 19 UART_TXD RX_MODEM
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14 20 UART_CTS RTS_MODEM
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15 21 UART_RTS CTS_MODEM
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16 22 UART_DTR GPIO3
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17 23 UART_DCD GPIO2
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18
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19 The interface signal names in Huawei's manual are given from the host's
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20 perspective (classic DTE-to-DCE paradigm), thus they are the opposite of the
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21 connected Calypso signal names. For the MODEM UART a complete 8-signal
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22 interface with full modem control is defined, but the Calypso only provides
c06cac606af3 gtm900/interface-signals: notes from connection tracing
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23 TxD & RxD, RTS & CTS, thus the other 4 modem control signals are GPIOs. The
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24 signals which are defined as DTR and DCD from the host's perspective are
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25 connected to GPIOs 3 and 2, respectively, just like on TI's C-Sample and
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26 D-Sample boards, whereas the choices of GPIOs for DSR and RI are Huawei's own
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27 arbitrary picks, as TI's development boards did not provide these signals.
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28
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29 Power control signals
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30 =====================
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31
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32 Interface pin 13 (called VDD in the manual) appears to be connected to the V-IO
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33 rail inside.
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34
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35 Interface pin 15 (PWON) is connected directly to Iota PWON as expected.
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36
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37 Interface pin 31 (called RST in the manual) appears to be connected to Iota
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38 nTESTRESET through the same transistor circuit as on TI's development boards,
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39 i.e., the signal brought out on the module interface is not raw nTESTRESET, but
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40 what we call XDS_RESET, originally meant to be driven by TI's XDS510 and XDS560
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41 "emulator" pods.
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42
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43 Other signals
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44 =============
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45
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46 Interface pin 14 (called ADC in the manual) is connected to Iota ADIN1.
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47
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48 Interface pin 32 (called LPG in the manual) is indeed connected to Calypso ball
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49 DSR_MODEM/LPG, which Huawei's firmware configures to be the LPG output.