FreeCalypso > hg > freecalypso-reveng
comparison gtm900/interface-signals @ 290:c06cac606af3
gtm900/interface-signals: notes from connection tracing
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Fri, 07 Jun 2019 20:20:49 +0000 |
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| 289:d6b65114b82d | 290:c06cac606af3 |
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| 1 UART interfaces | |
| 2 =============== | |
| 3 | |
| 4 Both Calypso UARTs are brought out on the GTM900 module interface as follows: | |
| 5 | |
| 6 Pin Name in manual Connected Calypso ball | |
| 7 11 RXD2 TX_IRDA | |
| 8 12 TXD2 RX_IRDA | |
| 9 ------------------------------- | |
| 10 16 UART_DSR GPIO1 | |
| 11 17 UART_RI GPIO0 | |
| 12 18 UART_RXD TX_MODEM | |
| 13 19 UART_TXD RX_MODEM | |
| 14 20 UART_CTS RTS_MODEM | |
| 15 21 UART_RTS CTS_MODEM | |
| 16 22 UART_DTR GPIO3 | |
| 17 23 UART_DCD GPIO2 | |
| 18 | |
| 19 The interface signal names in Huawei's manual are given from the host's | |
| 20 perspective (classic DTE-to-DCE paradigm), thus they are the opposite of the | |
| 21 connected Calypso signal names. For the MODEM UART a complete 8-signal | |
| 22 interface with full modem control is defined, but the Calypso only provides | |
| 23 TxD & RxD, RTS & CTS, thus the other 4 modem control signals are GPIOs. The | |
| 24 signals which are defined as DTR and DCD from the host's perspective are | |
| 25 connected to GPIOs 3 and 2, respectively, just like on TI's C-Sample and | |
| 26 D-Sample boards, whereas the choices of GPIOs for DSR and RI are Huawei's own | |
| 27 arbitrary picks, as TI's development boards did not provide these signals. | |
| 28 | |
| 29 Power control signals | |
| 30 ===================== | |
| 31 | |
| 32 Interface pin 13 (called VDD in the manual) appears to be connected to the V-IO | |
| 33 rail inside. | |
| 34 | |
| 35 Interface pin 15 (PWON) is connected directly to Iota PWON as expected. | |
| 36 | |
| 37 Interface pin 31 (called RST in the manual) appears to be connected to Iota | |
| 38 nTESTRESET through the same transistor circuit as on TI's development boards, | |
| 39 i.e., the signal brought out on the module interface is not raw nTESTRESET, but | |
| 40 what we call XDS_RESET, originally meant to be driven by TI's XDS510 and XDS560 | |
| 41 "emulator" pods. | |
| 42 | |
| 43 Other signals | |
| 44 ============= | |
| 45 | |
| 46 Interface pin 14 (called ADC in the manual) is connected to Iota ADIN1. | |
| 47 | |
| 48 Interface pin 32 (called LPG in the manual) is indeed connected to Calypso ball | |
| 49 DSR_MODEM/LPG, which Huawei's firmware configures to be the LPG output. |