FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/rf_fem_block.v @ 94:4502eec1e805
D405: use Nexperia part sourced from Digi-Key direct
The previously selected part was from a Digi-Key marketplace vendor,
and they seem to not actually have that part, as the order has been
in limbo for over a month - so I put in the time and effort to look
around, and found a readily available equivalent part from Nexperia.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 11 Jan 2022 19:11:22 +0000 |
parents | 3ed0f7a9c489 |
children |
rev | line source |
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9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /* |
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Venus: first version of Verilog for the Calypso core
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2 * This module encapsulates the RF FEM (quadband M034F) along with the PNP |
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3 * transistors and R/C footprints to GND for the control lines, and the cap |
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4 * on the antenna output. |
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5 */ |
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6 |
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7 module rf_fem_block (GND, VREG3, Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850, |
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8 RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2, |
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9 TX_LOW, TX_HIGH, ANT); |
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10 |
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parents:
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11 input GND, VREG3; |
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parents:
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12 input Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850; |
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parents:
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13 |
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Mychaela Falconia <falcon@freecalypso.org>
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14 output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2; |
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parents:
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15 input TX_LOW, TX_HIGH; |
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parents:
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16 inout ANT; |
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parents:
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17 |
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parents:
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18 wire ANT_before_cap; |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 wire V_TX_LOW, V_TX_HIGH, V_RX_850; |
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parents:
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20 |
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parents:
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21 /* transform control signals through PNP transistors */ |
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parents:
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22 |
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parents:
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23 transistor_slot PNP_FEM7 (.E(VREG3), .B(Ctrl_Tx_Low), .C(V_TX_LOW)); |
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parents:
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24 transistor_slot PNP_FEM8 (.E(VREG3), .B(Ctrl_Tx_High), .C(V_TX_HIGH)); |
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parents:
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25 transistor_slot PNP_FEM9 (.E(VREG3), .B(Ctrl_Rx_850), .C(V_RX_850)); |
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parents:
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26 |
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parents:
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27 /* instantiate the M034F */ |
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parents:
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28 |
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29 M034F M034F (.ANT(ANT_before_cap), |
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30 .GND(GND), |
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parents:
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31 .RX_LOW1(RX_LOW1), |
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parents:
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32 .RX_LOW2(RX_LOW2), |
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parents:
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33 .RX_DCS1(RX_DCS1), |
3ed0f7a9c489
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parents:
diff
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34 .RX_DCS2(RX_DCS2), |
3ed0f7a9c489
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parents:
diff
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35 .RX_PCS1(RX_PCS1), |
3ed0f7a9c489
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parents:
diff
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36 .RX_PCS2(RX_PCS2), |
3ed0f7a9c489
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parents:
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37 .TX_LOW(TX_LOW), |
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parents:
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38 .TX_HIGH(TX_HIGH), |
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parents:
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39 .V_TX_LOW(V_TX_LOW), |
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parents:
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40 .V_TX_HIGH(V_TX_HIGH), |
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parents:
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41 .V_RX_850(V_RX_850) |
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parents:
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42 ); |
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parents:
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43 |
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parents:
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44 capacitor C635 (ANT_before_cap, ANT); |
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parents:
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45 |
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parents:
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46 capacitor C645 (V_TX_LOW, GND); |
3ed0f7a9c489
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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47 capacitor C644 (V_TX_HIGH, GND); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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48 capacitor C643 (V_RX_850, GND); |
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parents:
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49 |
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50 endmodule |