FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/memory.v @ 87:96e02b1b2374

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change flash+RAM MCP to S71PL129N
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 06:43:39 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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1 module memory (GND, Vflash, Vsram,
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2 MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE,
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96e02b1b2374 change flash+RAM MCP to S71PL129N
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3 Flash_RST, CS_flash1, CS_flash2, CS_RAM);
9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 input GND, Vflash, Vsram;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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6 input [22:1] MCU_A;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 inout [15:0] MCU_D;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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8 input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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9 input Flash_RST;
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10 input CS_flash1, CS_flash2, CS_RAM;
9
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parents:
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11
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96e02b1b2374 change flash+RAM MCP to S71PL129N
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12 S71PL129N chip (.Flash_Vcc(Vflash),
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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13 .RAM_Vcc(Vsram),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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14 .Vss(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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15 .A(MCU_A),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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16 .DQ(MCU_D),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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17 .OE(MCU_nRD),
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parents:
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18 .WE(MCU_nWR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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19 .Flash_CE1(CS_flash1),
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96e02b1b2374 change flash+RAM MCP to S71PL129N
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20 .Flash_CE2(CS_flash2),
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parents:
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21 .Flash_RST(Flash_RST),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 .Flash_WP_ACC(Vflash),
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parents:
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23 .Flash_ready_busy(), /* no connect */
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24 .RAM_CE_actlow(CS_RAM),
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parents:
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25 .RAM_CE_acthigh(Vsram),
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parents:
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26 .RAM_UB(MCU_nBHE),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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27 .RAM_LB(MCU_nBLE)
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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28 );
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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29
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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30 /* bypass caps */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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31 capacitor C318 (Vsram, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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32 capacitor C322 (Vflash, GND);
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33
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34 endmodule