FreeCalypso > hg > freecalypso-schem2
annotate venus/src/primitives @ 35:971c05950675
starpoints in core: commit to using pcb-rnd intnoconn
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 22 Nov 2021 09:54:48 +0000 |
parents | 1d2b57d4f1c9 |
children | 9309cebe07b8 |
rev | line source |
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1 /* |
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2 * This file defines the primitives to be instantiated from the structural |
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3 * Verilog source for the board: IC package types, basic components and |
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4 * subpackages to be mapped later in the MCL binding step. |
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5 */ |
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6 |
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7 resistor numpins 2; |
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8 capacitor numpins 2; |
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9 inductor numpins 2; |
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10 rlc_generic numpins 2; /* "any" RLC for matching network topologies */ |
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11 |
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12 resistor_slot mapped_pins (side1, side2); |
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13 transistor_slot mapped_pins (E, B, C); |
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14 mosfet mapped_pins (G, S, D); |
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15 |
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16 /* TI packages */ |
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17 pkg_179GHH grid "pkg_179GHH.bgadef"; |
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18 pkg_100GGM grid "pkg_100GGM.bgadef"; |
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19 pkg_Rita_RF numpins 49; |
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20 pkg_TPA6203A1 mapped_pins (BYPASS, GND, In_neg, In_pos, SHUTDOWN, VDD, |
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21 Out_pos, Out_neg); |
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22 |
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23 /* non-TI RF components */ |
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24 pkg_RF3166 numpins 31; |
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25 pkg_M034F numpins 19; |
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26 |
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27 /* Flash+RAM MCP (two possibilities) */ |
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28 pkg_TLA064 grid "pkg_TLA064.bgadef"; |
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29 pkg_TLC056 grid "pkg_TLC056.bgadef"; |
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30 |
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31 /* misc IC packages */ |
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32 pkg_LQFP48 numpins 48; |
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33 pkg_IC_5pin numpins 5; |
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34 pkg_IC_8pin numpins 8; |
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35 pkg_XSON6 numpins 6; |
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36 |
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37 /* logic IC subpackages */ |
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38 buffer_slot_basic mapped_pins (A, Y); |
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39 buffer_slot_3state mapped_pins (A, nOE, Y); |
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40 logic_ic_common mapped_pins (Vcc, GND); |
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41 x541_common mapped_pins (Vcc, GND, nOE1, nOE2); |
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42 |
6
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43 /* crystal oscillator components */ |
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44 xtal_2pin_pkg numpins 2; |
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45 xtal_4pin_pkg numpins 4; |
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46 varactor_diode mapped_pins (A, C); |
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47 |
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48 /* |
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49 * The reference design we are copying calls for a couple of RF chip |
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50 * attenuators. They are symmetrical in that pins 1 and 2 are equally |
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51 * suitable as either the input or the output, but the package shape is |
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52 * asymmetrical, thus it is a PCB layout decision which pin will be the |
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53 * input and which will be the output. |
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54 * |
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55 * We shall use a mapped_pins primitive and two different pinout mappings |
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56 * at the MCL binding stage, to be selected at layout time. |
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57 */ |
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58 |
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59 chip_attenuator mapped_pins (In, Out, GND1, GND2); |
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60 |
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61 /* connectors */ |
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62 header_2pin numpins 2; |
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63 conn_3pin numpins 3; |
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64 header_14pin numpins 14; |
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65 pkg_SMA_F numpins 5; |
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66 pkg_TRRS_jack numpins 6; |
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67 conn_miniUSB_plus4 numpins 9; |
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68 |
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69 /* misc peripherals */ |
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70 pkg_SIM_socket numpins 8; |
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71 basic_LED mapped_pins (A, C); |
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72 misc_diode mapped_pins (A, C); |
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73 switch_2pin numpins 2; |
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74 |
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75 /* |
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76 * Resistor footprint with two extra "virtual pins" for sensing - see |
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77 * ../doc/Charging-circuit for explanation. |
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78 */ |
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79 |
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80 resistor_with_sense mapped_pins (side1_current, side1_sense, |
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81 side2_current, side2_sense); |
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82 |
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83 /* |
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84 * The following primitives are entirely non-physical EDA artifacts |
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85 * for star routing. |
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86 */ |
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87 starpoint_2way numpins 2; |
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88 starpoint_3way numpins 3; |