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annotate venus/doc/Charging-circuit @ 90:e8ce3b688723

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venus/doc/Flash+RAM: R372 addition documented
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 23:00:44 +0000
parents cf39d9352394
children
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1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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1 The battery charging circuit on FC Venus board is the one depicted on page 56
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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2 of this TI document:
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3
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4 ftp://ftp.freecalypso.org/pub/GSM/Calypso/APN0_120.pdf
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5
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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6 Specifically, it is the circuit depicted on the right side of Figure 7-5, the
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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7 circuit with the charging power source at the top and the battery at the bottom.
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8 Going from net VCHG (output of our charging control switch S701) to net VBAT
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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9 (battery +ve terminal), the charging circuit consists of Q401, D404 and R407
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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10 strung in series, with R406 adjoining between Q401 and D404. The exact location
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11 of this circuit on the board will be up to the PCB layout engineer, but we
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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12 expect that all 4 of the just-named components will be placed on the same side
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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13 of the board (either top or bottom), with surface traces (no vias) carrying the
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14 charging current (500 mA design intent) from each component to the next. It is
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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15 important to note that whichever side of the board this circuit is placed on,
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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16 it will NOT be located inside either of the two shieldcan areas.
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17
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18 Two signal traces VCCS and VBATS will need to run from wherever the charging
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19 circuit ends up residing on the board to corresponding U202 Iota chip terminals
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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20 inside the baseband core shieldcan. These traces do not carry current, instead
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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21 they are differential inputs to a voltage-measuring ADC, specifically measuring
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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22 the voltage drop across R407 and thus deducing the current that flows through
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23 the charging circuit at each given moment.
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24
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25 Galvanically VBAT (board-wide battery power distribution) and VBATS (one side
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26 of the differential pair measuring the voltage across R407) are the same net,
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27 but we would like them to be seen as two separate nets by our EDA tools, to
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28 facilitate proper routing. The Mother's idea is to use intnoconn feature of
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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29 pcb-rnd:
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30
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31 http://repo.hu/cgi-bin/pool.cgi?project=pcb-rnd&cmd=show&node=intnoconn
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32
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33 More specifically, the Mother's idea is that the subcircuit representing R407
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34 will have 4 terminals rather than 2, with terminal numbers assigned as follows:
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35
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36 Pin 1 = resistor side 1, surface layer
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cf39d9352394 R407 intnoconn: use different terminal numbering on further thought
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37 Pin 2 = resistor side 2, surface layer
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38 Pin 3 = resistor side 1, inner layer
33
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39 Pin 4 = resistor side 2, inner layer
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40
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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41 The idea is to include in-pad microvias going one layer down inside the
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cf39d9352394 R407 intnoconn: use different terminal numbering on further thought
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42 subcircuit, and put terminals 3 and 4 on the inner layer. Terminals 1 & 3 will
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43 form one intnoconn group, and terminals 2 & 4 will form the other intnoconn
33
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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44 group. Surface traces carrying the charging current will connect to terminals
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cf39d9352394 R407 intnoconn: use different terminal numbering on further thought
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45 1 and 2, whereas sensing nets VCCS and VBATS will connect to terminals 3 and 4
33
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46 on the inner layer.
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47
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48 Our current ueda source implements this idea at the netlist level; creation of
1d2b57d4f1c9 intnoconn approach to charging current sense resistor
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49 the corresponding pcb-rnd subcircuit remains TBD.