comparison venus/src/core/rfmatch_rita2pa_hb.v @ 9:3ed0f7a9c489

Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /* RF Tx path from Rita to PA, high bands */
2
3 module rfmatch_rita2pa_hb (In, Out, GND, VREG3);
4
5 input In;
6 output Out;
7 input GND, VREG3;
8
9 wire mid;
10
11 inductor L600 (In, VREG3);
12 capacitor C600 (In, mid);
13 chip_attenuator R601 (mid, Out, GND, GND);
14
15 endmodule