view venus/src/core/rfmatch_rita2pa_hb.v @ 9:3ed0f7a9c489

Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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/* RF Tx path from Rita to PA, high bands */

module rfmatch_rita2pa_hb (In, Out, GND, VREG3);

input In;
output Out;
input GND, VREG3;

wire mid;

inductor L600 (In, VREG3);
capacitor C600 (In, mid);
chip_attenuator R601 (mid, Out, GND, GND);

endmodule