FreeCalypso > hg > freecalypso-schem2
comparison venus/src/core/memory.v @ 87:96e02b1b2374
change flash+RAM MCP to S71PL129N
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 10 Dec 2021 06:43:39 +0000 |
parents | 3ed0f7a9c489 |
children |
comparison
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inserted
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86:adc84e0e98d6 | 87:96e02b1b2374 |
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1 module memory (GND, Vflash, Vsram, | 1 module memory (GND, Vflash, Vsram, |
2 MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE, | 2 MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE, |
3 Flash_RST, CS_flash1, CS_RAM); | 3 Flash_RST, CS_flash1, CS_flash2, CS_RAM); |
4 | 4 |
5 input GND, Vflash, Vsram; | 5 input GND, Vflash, Vsram; |
6 input [22:1] MCU_A; | 6 input [22:1] MCU_A; |
7 inout [15:0] MCU_D; | 7 inout [15:0] MCU_D; |
8 input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE; | 8 input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE; |
9 input Flash_RST; | 9 input Flash_RST; |
10 input CS_flash1, CS_RAM; | 10 input CS_flash1, CS_flash2, CS_RAM; |
11 | 11 |
12 S71PL064J chip (.Flash_Vcc(Vflash), | 12 S71PL129N chip (.Flash_Vcc(Vflash), |
13 .RAM_Vcc(Vsram), | 13 .RAM_Vcc(Vsram), |
14 .Vss(GND), | 14 .Vss(GND), |
15 .A(MCU_A), | 15 .A(MCU_A), |
16 .DQ(MCU_D), | 16 .DQ(MCU_D), |
17 .OE(MCU_nRD), | 17 .OE(MCU_nRD), |
18 .WE(MCU_nWR), | 18 .WE(MCU_nWR), |
19 .Flash_CE1(CS_flash1), | 19 .Flash_CE1(CS_flash1), |
20 .Flash_CE2(CS_flash2), | |
20 .Flash_RST(Flash_RST), | 21 .Flash_RST(Flash_RST), |
21 .Flash_WP_ACC(Vflash), | 22 .Flash_WP_ACC(Vflash), |
22 .Flash_ready_busy(), /* no connect */ | 23 .Flash_ready_busy(), /* no connect */ |
23 .RAM_CE_actlow(CS_RAM), | 24 .RAM_CE_actlow(CS_RAM), |
24 .RAM_CE_acthigh(Vsram), | 25 .RAM_CE_acthigh(Vsram), |