--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/audio_main.v	Wed Dec 01 02:22:39 2021 +0000
@@ -0,0 +1,51 @@
+/*
+ * This Verilog module encapsulates our main audio channel.
+ */
+
+module audio_main (GND, EARN, EARP, MICBIAS, MICIN, MICIP);
+
+input GND;
+input EARN, EARP;
+input MICBIAS;
+output MICIN, MICIP;
+
+/* internal wires */
+
+wire EARN_jack, EARP_jack, MIC_jack;
+
+/* instantiate the jack */
+
+trrs_jack jack (.T(EARP_jack),
+		.R(MIC_jack),
+		.R2(EARN_jack),
+		.S(GND),
+		.T_sw(),	/* not used */
+		.R_sw()		/* not used */
+	);
+
+/* earpiece path filter caps */
+
+capacitor C15 (EARP, EARN);
+capacitor C16 (EARP, GND);
+capacitor C17 (EARP, GND);
+capacitor C18 (EARN, GND);
+capacitor C19 (EARN, GND);
+
+/* earpiece path filter inductors */
+
+inductor L1 (EARP, EARP_jack);
+inductor L2 (EARN, EARN_jack);
+
+/* microphone input circuit */
+
+capacitor C13 (MICBIAS, GND);
+
+resistor R9 (MICBIAS, MIC_jack);
+capacitor C14 (MIC_jack, GND);
+
+capacitor C12 (MICBIAS,  MICIP);
+capacitor C21 (MIC_jack, MICIN);
+
+capacitor C32 (MICIP, MICIN);
+
+endmodule