diff venus/src/core/iota_100ggm.v @ 9:3ed0f7a9c489

Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/iota_100ggm.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,175 @@
+module iota_100ggm (ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
+		    BDLIM, BDLIP, BDLQM, BDLQP, BDR, BDX, BFSR, BFSX, BULIM,
+		    BULIP, BULQM, BULQP, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
+		    DBBSRST, EARN, EARP, GNDA, GNDAV, GNDD, GNDL1, GNDL2,
+		    HSMICBIAS, HSMICP, HSO, IBIAS, ICTL, INT1, INT2, ITWAKEUP,
+		    LEDA, LEDB1, LEDB2, LEDC, MICBIAS, MICIN, MICIP, ON_nOFF,
+		    PCHG, PWON, REFGND, RESPWONz, RPWON, SIMCK, SIMIO, SIMRST,
+		    TCK, TDI, TDO, TDR, TEN, TEST3, TEST4, TESTRSTz, TESTV,
+		    TMS, UDR, UDX, UEN, UPR, VBACKUP, VBAT, VBATS, VCABB, VCCS,
+		    VCDBB, VCHG, VCIO1, VCIO2, VCK, VCMEM, VCRAM, VDR, VDX,
+		    VFS, VLMEM, VLRTC, VRABB, VRDBB, VREF, VRIO1, VRIO2, VRMEM,
+		    VRRAM, VRRTC, VRSIM, VSDBB, VXRTC);
+
+input ADIN1, ADIN2, ADIN3, ADIN4;
+output AFC, APC, DAC;
+
+input AUXI;
+output AUXON, AUXOP;
+output EARN, EARP;
+output HSMICBIAS, HSO;
+input HSMICP;
+output MICBIAS;
+input MICIN, MICIP;
+
+input BDLIM, BDLIP, BDLQM, BDLQP;
+output BULIM, BULIP, BULQM, BULQP;
+
+input BDR, BFSR;
+output BDX, BFSX;
+input TDR, TEN;
+input UDR, UEN;
+output UDX;
+output VCK, VDX, VFS;
+input VDR;
+
+input CK13M, CK32K, ITWAKEUP;
+output INT1, INT2;
+output ON_nOFF, RESPWONz;
+
+input DBBSCK, DBBSRST;
+inout DBBSIO;
+
+input GNDA, GNDAV, GNDD, GNDL1, GNDL2;
+
+inout IBIAS, VREF, REFGND;
+
+input PWON, RPWON;
+output ICTL, PCHG;
+
+output LEDA, LEDB1, LEDB2, LEDC;
+
+output SIMCK, SIMRST;
+inout SIMIO;
+
+input TCK, TDI, TMS;
+output TDO;
+inout TEST3, TEST4;
+input TESTRSTz;
+output TESTV;
+
+inout UPR;
+input VBACKUP, VBAT, VBATS, VCABB, VCCS, VCDBB, VCHG, VCIO1, VCIO2;
+input VCMEM, VCRAM;
+
+input VLMEM, VLRTC;
+output VRABB, VRDBB, VRIO1, VRIO2, VRMEM, VRRAM, VRRTC, VRSIM;
+
+input VSDBB;
+inout VXRTC;
+
+/* instantiate the package; the mapping of signals to balls is defined here */
+
+pkg_100GGM pkg (.B6(ADIN1),
+		.A6(ADIN2),
+		.C7(ADIN3),
+		.C6(ADIN4),
+		.J4(AFC),
+		.K4(APC),
+		.G7(AUXI),
+		.K10(AUXON),
+		.K9(AUXOP),
+		.F10(BDLIM),
+		.F9(BDLIP),
+		.E9(BDLQM),
+		.E10(BDLQP),
+		.J3(BDR),
+		.J2(BDX),
+		.H3(BFSR),
+		.K2(BFSX),
+		.D10(BULIM),
+		.D9(BULIP),
+		.C9(BULQM),
+		.C10(BULQP),
+		.E4(CK13M),
+		.E2(CK32K),
+		.H4(DAC),
+		.F4(DBBSCK),
+		.E5(DBBSIO),
+		.G4(DBBSRST),
+		.J10(EARN),
+		.J9(EARP),
+		.G10(GNDA),
+		.G6(GNDAV),
+		.A3(GNDD),
+		.B9(GNDL1),
+		.A9(GNDL2),
+		.K8(HSMICBIAS),
+		.K7(HSMICP),
+		.H9(HSO),
+		.B7(IBIAS),
+		.D6(ICTL),
+		.H6(INT1),
+		.E6(INT2),
+		.D2(ITWAKEUP),
+		.B8(LEDA),
+		.B10(LEDB1),
+		.A10(LEDB2),
+		.C8(LEDC),
+		.J8(MICBIAS),
+		.H7(MICIN),
+		.J7(MICIP),
+		.E3(ON_nOFF),
+		.B5(PCHG),
+		.F8(PWON),
+		.A7(REFGND),
+		.D3(RESPWONz),
+		.F7(RPWON),
+		.C4(SIMCK),
+		.B3(SIMIO),
+		.D4(SIMRST),
+		.D8(TCK),
+		.D7(TDI),
+		.E7(TDO),
+		.G3(TDR),
+		.H1(TEN),
+		.J6(TEST3),
+		.F6(TEST4),
+		.H8(TESTRSTz),
+		.G8(TESTV),
+		.E8(TMS),
+		.K5(UDR),
+		.J5(UDX),
+		.K6(UEN),
+		.C2(UPR),
+		.E1(VBACKUP),
+		.A4(VBAT),
+		.C5(VBATS),
+		.G9(VCABB),
+		.D5(VCCS),
+		.K1(VCDBB),
+		.A5(VCHG),
+		.A2(VCIO1),
+		.A1(VCIO2),
+		.K3(VCK),
+		.G2(VCMEM),
+		.F2(VCRAM),
+		.F5(VDR),
+		.H5(VDX),
+		.G5(VFS),
+		.F3(VLMEM),
+		.C3(VLRTC),
+		.H10(VRABB),
+		.J1(VRDBB),
+		.A8(VREF),
+		.B2(VRIO1),
+		.B1(VRIO2),
+		.G1(VRMEM),
+		.F1(VRRAM),
+		.D1(VRRTC),
+		.B4(VRSIM),
+		.H2(VSDBB),
+		.C1(VXRTC)
+	);
+
+endmodule