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view venus/src/core/clock_rf2dbb.v @ 13:975b9b7ec712

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Venus MCL: add 74LVC125A for Calypso UART inputs
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 18:57:57 +0000
parents 3ed0f7a9c489
children
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module clock_rf2dbb (In, Out);

input In;
output Out;

wire mid;

resistor R251 (In, mid);

capacitor C253 (mid, Out);

endmodule