view venus/src/periph/trrs_jack.v @ 68:ef00bcf4a7ee

MCL: assign value to all capacitors
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 05:53:13 +0000
parents 3afd172b83e1
children
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/*
 * This Verilog module encapsulates the physical PCB footprint pinout
 * of the TRRS jack part we are using.
 */

module trrs_jack (T, R, R2, S, T_sw, R_sw);

inout T, R, R2, S;
inout T_sw, R_sw;

pkg_TRRS_jack pkg (.pin_1(S),
		   .pin_2(T),
		   .pin_3(R),
		   .pin_4(R2),
		   .pin_5(T_sw),
		   .pin_6(R_sw)
	);

endmodule