FreeCalypso > hg > freecalypso-schem2

changeset 9:3ed0f7a9c489

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents d23dae52cd7b
children 5ee03a306da3
files venus/src/core/M034F.v venus/src/core/RF3166.v venus/src/core/S71PL064J.v venus/src/core/abb_block.v venus/src/core/abb_rc_network.v venus/src/core/baseband.v venus/src/core/calypso_179ghh.v venus/src/core/clock_rf2dbb.v venus/src/core/core.v venus/src/core/dbb_block.v venus/src/core/int_vcxo_passive.v venus/src/core/iota_100ggm.v venus/src/core/memory.v venus/src/core/rf_fem_block.v venus/src/core/rf_pa_block.v venus/src/core/rf_section.v venus/src/core/rfmatch_fem2rita_dcs.v venus/src/core/rfmatch_fem2rita_low.v venus/src/core/rfmatch_fem2rita_pcs.v venus/src/core/rfmatch_pa2fem_pi.v venus/src/core/rfmatch_rita2pa_hb.v venus/src/core/rfmatch_rita2pa_lb.v venus/src/core/rita_rf_chip.v venus/src/core/rita_vcxo_int.v venus/src/core/rita_wrap.v venus/src/core/xtal_32khz_wrap.v
diffstat 26 files changed, 2246 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/M034F.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,35 @@
+module M034F (ANT, GND, RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
+		TX_LOW, TX_HIGH, V_TX_LOW, V_TX_HIGH, V_RX_850);
+
+inout ANT;
+input GND;
+
+output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
+input TX_LOW, TX_HIGH;
+
+input V_TX_LOW, V_TX_HIGH, V_RX_850;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_M034F pkg  (.pin_1(ANT),
+		.pin_2(GND),
+		.pin_3(TX_HIGH),
+		.pin_4(GND),
+		.pin_5(GND),
+		.pin_6(TX_LOW),
+		.pin_7(V_TX_LOW),
+		.pin_8(V_TX_HIGH),
+		.pin_9(V_RX_850),
+		.pin_10(RX_DCS1),
+		.pin_11(RX_DCS2),
+		.pin_12(RX_PCS1),
+		.pin_13(RX_PCS2),
+		.pin_14(RX_LOW1),
+		.pin_15(RX_LOW2),
+		.pin_16(GND),
+		.pin_17(GND),
+		.pin_18(GND),
+		.pin_19(GND)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/RF3166.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,44 @@
+module RF3166 (HB_RF_in, Band_Select, Tx_Enable, Vbatt, GND, Vramp, LB_RF_in,
+		LB_RF_out, HB_RF_out);
+
+input LB_RF_in, HB_RF_in;
+input Band_Select, Tx_Enable;
+input GND, Vbatt, Vramp;
+output LB_RF_out, HB_RF_out;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_RF3166 pkg (.pin_1(HB_RF_in),
+		.pin_2(Band_Select),
+		.pin_3(Tx_Enable),
+		.pin_4(Vbatt),
+		.pin_5(GND),
+		.pin_6(Vramp),
+		.pin_7(LB_RF_in),
+		.pin_8(LB_RF_out),
+		.pin_9(HB_RF_out),
+		.pin_10(GND),
+		.pin_11(GND),
+		.pin_12(GND),
+		.pin_13(GND),
+		.pin_14(GND),
+		.pin_15(GND),
+		.pin_16(GND),
+		.pin_17(GND),
+		.pin_18(GND),
+		.pin_19(GND),
+		.pin_20(GND),
+		.pin_21(GND),
+		.pin_22(GND),
+		.pin_23(GND),
+		.pin_24(GND),
+		.pin_25(GND),
+		.pin_26(GND),
+		.pin_27(GND),
+		.pin_28(GND),
+		.pin_29(GND),
+		.pin_30(GND),
+		.pin_31(GND)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/S71PL064J.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,75 @@
+module S71PL064J (Flash_Vcc, RAM_Vcc, Vss,
+		  A, DQ, OE, WE,
+		  Flash_CE1, Flash_RST,
+		  Flash_WP_ACC, Flash_ready_busy,
+		  RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);
+
+input Flash_Vcc, RAM_Vcc, Vss;
+input [21:0] A;
+inout [15:0] DQ;
+input OE, WE;
+input Flash_CE1, Flash_RST, Flash_WP_ACC;
+output Flash_ready_busy;
+input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;
+
+/* instantiate the package; the mapping of signals to balls is defined here */
+
+pkg_TLC056 pkg (.A2(A[7]),
+		.A3(RAM_LB),
+		.A4(Flash_WP_ACC),
+		.A5(WE),
+		.A6(A[8]),
+		.A7(A[11]),
+		.B1(A[3]),
+		.B2(A[6]),
+		.B3(RAM_UB),
+		.B4(Flash_RST),
+		.B5(RAM_CE_acthigh),
+		.B6(A[19]),
+		.B7(A[12]),
+		.B8(A[15]),
+		.C1(A[2]),
+		.C2(A[5]),
+		.C3(A[18]),
+		.C4(Flash_ready_busy),
+		.C5(A[20]),
+		.C6(A[9]),
+		.C7(A[13]),
+		.C8(A[21]),
+		.D1(A[1]),
+		.D2(A[4]),
+		.D3(A[17]),
+		.D6(A[10]),
+		.D7(A[14]),
+		.D8(),		/* no connect */
+		.E1(A[0]),
+		.E2(Vss),
+		.E3(DQ[1]),
+		.E6(DQ[6]),
+		.E7(),		/* no connect */
+		.E8(A[16]),
+		.F1(Flash_CE1),
+		.F2(OE),
+		.F3(DQ[9]),
+		.F4(DQ[3]),
+		.F5(DQ[4]),
+		.F6(DQ[13]),
+		.F7(DQ[15]),
+		.F8(),		/* no connect */
+		.G1(RAM_CE_actlow),
+		.G2(DQ[0]),
+		.G3(DQ[10]),
+		.G4(Flash_Vcc),
+		.G5(RAM_Vcc),
+		.G6(DQ[12]),
+		.G7(DQ[7]),
+		.G8(Vss),
+		.H2(DQ[8]),
+		.H3(DQ[2]),
+		.H4(DQ[11]),
+		.H5(),		/* no connect */
+		.H6(DQ[5]),
+		.H7(DQ[14])
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/abb_block.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,238 @@
+/*
+ * This module encapsulates the Iota ABB chip plus the following:
+ *
+ * - bypass capacitors on the VBAT input and the regulator outputs
+ * - all GND connections
+ * - IBIAS and VREF external components
+ * - UPR, VLMEM, VLRTC and everything connected to them
+ * - pull-up of SIM_IO to VSIM
+ * - cap on the AFC output
+ * - RC network joining BDL[IQ][MP] and BUL[IQ][MP]
+ * - VBACKUP resistor to GND in this FC Venus version
+ *
+ * All other Iota signals are passed through untouched.
+ */
+
+module abb_block (GND, VBAT, VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc,
+		  nRESPWON, nTESTRESET,
+		  Analog_IM, Analog_IP, Analog_QM, Analog_QP,
+		  ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
+		  BDR, BDX, BFSR, BFSX, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
+		  DBBSRST, EARN, EARP,
+		  HSMICBIAS, HSMICP, HSO, ICTL, INT1, INT2, ITWAKEUP,
+		  LED_A, LED_B, LED_C, MICBIAS, MICIN, MICIP, ON_nOFF,
+		  PCHG, PWON, RPWON,
+		  TCK, TDI, TDO, TDR, TEN, TMS, UDR, UDX, UEN,
+		  VBATS, VCCS, VCHG, VCK, VDR, VDX, VFS,
+		  SIM_IO, SIM_CLK, SIM_RST);
+
+input GND, VBAT;
+output VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc;
+
+output nRESPWON;
+input nTESTRESET;
+
+inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
+
+input ADIN1, ADIN2, ADIN3, ADIN4;
+output AFC, APC, DAC;
+
+input AUXI;
+output AUXON, AUXOP;
+output EARN, EARP;
+output HSMICBIAS, HSO;
+input HSMICP;
+output MICBIAS;
+input MICIN, MICIP;
+
+input BDR, BFSR;
+output BDX, BFSX;
+input TDR, TEN;
+input UDR, UEN;
+output UDX;
+output VCK, VDX, VFS;
+input VDR;
+
+input CK13M, CK32K, ITWAKEUP;
+output INT1, INT2;
+output ON_nOFF;
+
+input DBBSCK, DBBSRST;
+inout DBBSIO;
+
+input PWON, RPWON;
+output ICTL, PCHG;
+
+output LED_A, LED_B, LED_C;
+
+output SIM_CLK, SIM_RST;
+inout SIM_IO;
+
+input TCK, TDI, TMS;
+output TDO;
+
+input VBATS, VCCS, VCHG;
+
+/* nets inside this module */
+wire UPR, VLMEM, Vabb;
+wire IBIAS, VREF;
+wire BULIM, BULIP, BULQM, BULQP;
+wire VBACKUP;
+
+/* instantiate the Iota! */
+
+iota_100ggm iota (.ADIN1(ADIN1),
+		  .ADIN2(ADIN2),
+		  .ADIN3(ADIN3),
+		  .ADIN4(ADIN4),
+		  .AFC(AFC),
+		  .APC(APC),
+		  .AUXI(AUXI),
+		  .AUXON(AUXON),
+		  .AUXOP(AUXOP),
+		  .BDLIM(Analog_IM),
+		  .BDLIP(Analog_IP),
+		  .BDLQM(Analog_QM),
+		  .BDLQP(Analog_QP),
+		  .BDR(BDR),
+		  .BDX(BDX),
+		  .BFSR(BFSR),
+		  .BFSX(BFSX),
+		  .BULIM(BULIM),
+		  .BULIP(BULIP),
+		  .BULQM(BULQM),
+		  .BULQP(BULQP),
+		  .CK13M(CK13M),
+		  .CK32K(CK32K),
+		  .DAC(DAC),
+		  .DBBSCK(DBBSCK),
+		  .DBBSIO(DBBSIO),
+		  .DBBSRST(DBBSRST),
+		  .EARN(EARN),
+		  .EARP(EARP),
+		  .GNDA(GND),
+		  .GNDAV(GND),
+		  .GNDD(GND),
+		  .GNDL1(GND),
+		  .GNDL2(GND),
+		  .HSMICBIAS(HSMICBIAS),
+		  .HSMICP(HSMICP),
+		  .HSO(HSO),
+		  .IBIAS(IBIAS),
+		  .ICTL(ICTL),
+		  .INT1(INT1),
+		  .INT2(INT2),
+		  .ITWAKEUP(ITWAKEUP),
+		  .LEDA(LED_A),
+		  .LEDB1(LED_B),
+		  .LEDB2(LED_B),
+		  .LEDC(LED_C),
+		  .MICBIAS(MICBIAS),
+		  .MICIN(MICIN),
+		  .MICIP(MICIP),
+		  .ON_nOFF(ON_nOFF),
+		  .PCHG(PCHG),
+		  .PWON(PWON),
+		  .REFGND(GND),
+		  .RESPWONz(nRESPWON),
+		  .RPWON(RPWON),
+		  .SIMCK(SIM_CLK),
+		  .SIMIO(SIM_IO),
+		  .SIMRST(SIM_RST),
+		  .TCK(TCK),
+		  .TDI(TDI),
+		  .TDO(TDO),
+		  .TDR(TDR),
+		  .TEN(TEN),
+		  .TEST3(),	/* no connect */
+		  .TEST4(),	/* ditto */
+		  .TESTRSTz(nTESTRESET),
+		  .TESTV(),	/* no connect */
+		  .TMS(TMS),
+		  .UDR(UDR),
+		  .UDX(UDX),
+		  .UEN(UEN),
+		  .UPR(UPR),
+		  .VBACKUP(VBACKUP),
+		  .VBAT(VBAT),
+		  .VBATS(VBATS),
+		  .VCABB(VBAT),
+		  .VCCS(VCCS),
+		  .VCDBB(VBAT),
+		  .VCHG(VCHG),
+		  .VCIO1(VBAT),
+		  .VCIO2(VBAT),
+		  .VCK(VCK),
+		  .VCMEM(VBAT),
+		  .VCRAM(VBAT),
+		  .VDR(VDR),
+		  .VDX(VDX),
+		  .VFS(VFS),
+		  .VLMEM(VLMEM),
+		  .VLRTC(GND),
+		  .VRABB(Vabb),
+		  .VRDBB(Vdbb),
+		  .VREF(VREF),
+		  .VRIO1(Vio),
+		  .VRIO2(Vio),
+		  .VRMEM(Vflash),
+		  .VRRAM(Vsram),
+		  .VRRTC(Vrtc),
+		  .VRSIM(VSIM),
+		  .VSDBB(Vdbb),
+		  .VXRTC()	/* no connect */
+	);
+
+/* power bypass caps per Leonardo schematics */
+
+/* VBAT input */
+capacitor C220 (VBAT, GND);
+capacitor C221 (VBAT, GND);
+
+/* regulator outputs */
+capacitor C213 (Vabb, GND);
+capacitor C214 (Vdbb, GND);
+capacitor C215 (Vio, GND);
+capacitor C216 (Vflash, GND);
+capacitor C217 (Vsram, GND);
+capacitor C218 (VSIM, GND);
+capacitor C219 (Vrtc, GND);
+
+/* UPR bypass cap */
+capacitor C208 (UPR, GND);
+
+/*
+ * VLMEM is pulled up to UPR, and we are eliminating the pull-down option
+ * on FC Venus - our LCD wiring is incompatible with 1.8V MEMIF.
+ */
+resistor R209 (VLMEM, UPR);
+
+/* nTESTRESET also needs to be pulled up to UPR */
+resistor R208 (nTESTRESET, UPR);
+
+/* IBIAS and VREF */
+resistor R204 (IBIAS, GND);
+capacitor C204 (VREF, GND);
+
+/* pull-up on SIM_IO to VSIM */
+resistor R206 (SIM_IO, VSIM);
+
+/* cap on AFC output */
+capacitor C205 (AFC, GND);
+
+/* RC network joining BDL[IQ][MP] and BUL[IQ][MP] */
+
+abb_rc_network abb_rc_network ( .IM_bidir(Analog_IM),
+				.IP_bidir(Analog_IP),
+				.QM_bidir(Analog_QM),
+				.QP_bidir(Analog_QP),
+				.IM_abbout(BULIM),
+				.IP_abbout(BULIP),
+				.QM_abbout(BULQM),
+				.QP_abbout(BULQP)
+		);
+
+/* VBACKUP pull-down to GND */
+resistor VBACKUP_pull_down (VBACKUP, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/abb_rc_network.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,34 @@
+/*
+ * In the Leonardo schematics there is an RC network in the analog I&Q
+ * signal path between the uplink (BUL[IQ][MP]) outputs from the ABB
+ * and the bidirectional signals which connect directly to the RF xcvr
+ * and to Iota's downlink (BDL[IQ][MP]) inputs.
+ *
+ * This structural Verilog module encapsulates the RC network in question.
+ */
+
+module abb_rc_network (IM_bidir, IP_bidir, QM_bidir, QP_bidir,
+			IM_abbout, IP_abbout, QM_abbout, QP_abbout);
+
+inout IM_bidir, IP_bidir, QM_bidir, QP_bidir;
+input IM_abbout, IP_abbout, QM_abbout, QP_abbout;
+
+wire IM_mid, IP_mid, QM_mid, QP_mid;
+
+/* resistors on the outputs from the ABB */
+resistor_slot R295A (IM_abbout, IM_mid);
+resistor_slot R295B (IP_abbout, IP_mid);
+resistor_slot R295C (QP_abbout, QP_mid);
+resistor_slot R295D (QM_abbout, QM_mid);
+
+/* capacitors in the middle */
+capacitor C295 (QM_mid, QP_mid);
+capacitor C296 (IM_mid, IP_mid);
+
+/* resistors joining with the bidirectional lines */
+resistor_slot R296A (IM_mid, IM_bidir);
+resistor_slot R296B (IP_mid, IP_bidir);
+resistor_slot R296C (QP_mid, QP_bidir);
+resistor_slot R296D (QM_mid, QM_bidir);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/baseband.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,267 @@
+/*
+ * This module encapsulates the DBB, the ABB and the connections between
+ * them.  It approximately corresponds to the "200 - Baseband" sheet
+ * in the original Leonardo schematics.
+ */
+
+module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram,
+		 PWON, RPWON, nTESTRESET, ON_nOFF, CLKTCXO_IN,
+		 TDI, TDO, TCK, TMS,
+		 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP,
+		 MCU_nBLE, MCU_nBHE, MCU_nCS,
+		 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
+		 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
+		 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
+		 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
+		 KBC, KBR, BU_PWT, LT_PWL,
+		 GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT,
+		 GPIO8, GPIO13,
+		 ADIN1, ADIN2, ADIN3, ADIN4, DAC,
+		 AUXI, AUXON, AUXOP, EARN, EARP, HSMICBIAS, HSMICP, HSO,
+		 MICBIAS, MICIN, MICIP,
+		 LED_A, LED_B, LED_C,
+		 ICTL, PCHG, VBATS, VCCS, VCHG,
+		 SIM_IO, SIM_CLK, SIM_RST,
+		 Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC,
+		 TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT);
+
+input GND, VBAT;
+output VSIM, Vio, Vflash, Vsram;
+
+input PWON, RPWON, nTESTRESET;
+output ON_nOFF;
+
+input CLKTCXO_IN;
+
+input TDI, TCK, TMS;
+output TDO;
+
+output [22:0] MCU_A;
+inout [15:0] MCU_D;
+output MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP, MCU_nBLE, MCU_nBHE;
+output [4:0] MCU_nCS;
+
+output SCLK, SDO, nSCS1;
+inout SDI_SDA, nSCS0_SCL;
+
+output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
+input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
+inout DSR_LPG;
+
+output MCSI_TXD;
+input MCSI_RXD;
+inout MCSI_CLK, MCSI_FSYNCH;
+
+output [4:0] KBC;
+input [4:0] KBR;
+output BU_PWT, LT_PWL;
+
+inout GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, GPIO8, GPIO13;
+
+input ADIN1, ADIN2, ADIN3, ADIN4;
+output DAC;
+
+input AUXI;
+output AUXON, AUXOP;
+output EARN, EARP;
+output HSMICBIAS, HSO;
+input HSMICP;
+output MICBIAS;
+input MICIN, MICIP;
+
+output LED_A, LED_B, LED_C;
+
+output ICTL, PCHG;
+input VBATS, VCCS, VCHG;
+
+output SIM_CLK, SIM_RST;
+inout SIM_IO;
+
+inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
+output AFC, APC;
+output TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita;
+output [11:0] TSPACT;
+
+/* nets between DBB and ABB */
+wire Vdbb, Vrtc;
+wire CLK13M_OUT, CLK32K_OUT, nRESPWON, IT_WAKEUP;
+wire EXT_FIQ, EXT_IRQ;
+wire TSPEN_Iota;
+
+/* Baseband serial port */
+wire BSP_dbb2abb_data, BSP_dbb2abb_sync;
+wire BSP_abb2dbb_data, BSP_abb2dbb_sync;
+
+/* Voiceband serial port */
+wire VSP_DL_data, VSP_UL_data;
+wire VSP_clock, VSP_sync;
+
+/* MCU serial port */
+wire USP_dbb2abb_data, USP_abb2dbb_data, USP_enable;
+
+/* SIM interface at Vio */
+wire DBBSIO, DBBSCLK, DBBSRST;
+
+/* instantiate the DBB and ABB blocks! */
+
+dbb_block dbb ( .GND(GND),
+		.Vdbb(Vdbb),
+		.Vio(Vio),
+		.Vflash(Vflash),
+		.Vrtc(Vrtc),
+		.TSPCLKX(TSPCLK),
+		.TSPDO(TSPDO),
+		.TSPDI_IO4(GPIO4),
+		.TSPEN[0](TSPEN_Iota),
+		.TSPEN[1](),		/* no connect */
+		.TSPEN[2](TSPEN_Rita),
+		.TSPEN[3](),		/* no connect */
+		.TSPACT(TSPACT),
+		.DATA(MCU_D),
+		.ADD(MCU_A),
+		.RnW(MCU_RnW),
+		.nFWE(MCU_nFWE),
+		.nFOE(MCU_nFOE),
+		.FDP(MCU_FDP),
+		.nBLE(MCU_nBLE),
+		.nBHE(MCU_nBHE),
+		.nCS(MCU_nCS),
+		.SCLK(SCLK),
+		.SDO(SDO),
+		.SDI_SDA(SDI_SDA),
+		.nSCS0_SCL(nSCS0_SCL),
+		.nSCS1(nSCS1),
+		.TX_IRDA(TX_IRDA),
+		.RX_IRDA(RX_IRDA),
+		.TXIR_IRDA(TXIR_IRDA),
+		.RXIR_IRDA(RXIR_IRDA),
+		.SD_IRDA(SD_IRDA),
+		.TX_MODEM(TX_MODEM),
+		.RX_MODEM(RX_MODEM),
+		.RTS_MODEM(RTS_MODEM),
+		.CTS_MODEM(CTS_MODEM),
+		.DSR_LPG(DSR_LPG),
+		.MCSI_TXD(MCSI_TXD),
+		.MCSI_RXD(MCSI_RXD),
+		.MCSI_CLK(MCSI_CLK),
+		.MCSI_FSYNCH(MCSI_FSYNCH),
+		.KBC(KBC),
+		.KBR(KBR),
+		.BU_PWT(BU_PWT),
+		.LT_PWL(LT_PWL),
+		.GPIO[0](GPIO0),
+		.GPIO[1](GPIO1),
+		.GPIO[2](GPIO2),
+		.GPIO[3](GPIO3),
+		.nRESET_OUT_IO7(GPIO7_RESETOUT),
+		.CLKTCXO(CLKTCXO_IN),
+		.CLK32K_OUT(CLK32K_OUT),
+		.CLK13M_OUT(CLK13M_OUT),
+		.nRESPWON(nRESPWON),
+		.EXT_FIQ(EXT_FIQ),
+		.EXT_IRQ(EXT_IRQ),
+		.TCXOEN(TCXOEN),
+		.RFEN(RFEN),
+		.ON_OFF(ON_nOFF),
+		.IT_WAKEUP(IT_WAKEUP),
+		.TDI(TDI),
+		.TDO(TDO),
+		.TCK(TCK),
+		.TMS(TMS),
+		.BFSR(BSP_abb2dbb_sync),
+		.BDR(BSP_abb2dbb_data),
+		.BFSX(BSP_dbb2abb_sync),
+		.BDX(BSP_dbb2abb_data),
+		.BCLKX_IO6(GPIO6),
+		.BCLKR_ARMCLK(GND),
+		.VDX(VSP_DL_data),
+		.VDR(VSP_UL_data),
+		.VFSRX(VSP_sync),
+		.VCLKRX(VSP_clock),
+		.MCUDI(USP_abb2dbb_data),
+		.MCUDO(USP_dbb2abb_data),
+		.MCUEN0(USP_enable),
+		.MCUEN1_IO8(GPIO8),
+		.MCUEN2_IO13(GPIO13),
+		.SIM_IO(DBBSIO),
+		.SIM_CLK(DBBSCLK),
+		.SIM_RST(DBBSRST)
+	);
+
+abb_block abb ( .GND(GND),
+		.VBAT(VBAT),
+		.VSIM(VSIM),
+		.Vdbb(Vdbb),
+		.Vio(Vio),
+		.Vflash(Vflash),
+		.Vsram(Vsram),
+		.Vrtc(Vrtc),
+		.nRESPWON(nRESPWON),
+		.nTESTRESET(nTESTRESET),
+		.Analog_IM(Analog_IM),
+		.Analog_IP(Analog_IP),
+		.Analog_QM(Analog_QM),
+		.Analog_QP(Analog_QP),
+		.ADIN1(ADIN1),
+		.ADIN2(ADIN2),
+		.ADIN3(ADIN3),
+		.ADIN4(ADIN4),
+		.AFC(AFC),
+		.APC(APC),
+		.AUXI(AUXI),
+		.AUXON(AUXON),
+		.AUXOP(AUXOP),
+		.BDR(BSP_dbb2abb_data),
+		.BDX(BSP_abb2dbb_data),
+		.BFSR(BSP_dbb2abb_sync),
+		.BFSX(BSP_abb2dbb_sync),
+		.CK13M(CLK13M_OUT),
+		.CK32K(CLK32K_OUT),
+		.DAC(DAC),
+		.DBBSCK(DBBSCLK),
+		.DBBSIO(DBBSIO),
+		.DBBSRST(DBBSRST),
+		.EARN(EARN),
+		.EARP(EARP),
+		.HSMICBIAS(HSMICBIAS),
+		.HSMICP(HSMICP),
+		.HSO(HSO),
+		.ICTL(ICTL),
+		.INT1(EXT_FIQ),
+		.INT2(EXT_IRQ),
+		.ITWAKEUP(IT_WAKEUP),
+		.LED_A(LED_A),
+		.LED_B(LED_B),
+		.LED_C(LED_C),
+		.MICBIAS(MICBIAS),
+		.MICIN(MICIN),
+		.MICIP(MICIP),
+		.ON_nOFF(ON_nOFF),
+		.PCHG(PCHG),
+		.PWON(PWON),
+		.RPWON(RPWON),
+		.TCK(),		/* no connect */
+		.TDI(),		/* no connect */
+		.TDO(),		/* no connect */
+		.TDR(TSPDO),
+		.TEN(TSPEN_Iota),
+		.TMS(),		/* no connect */
+		.UDR(USP_dbb2abb_data),
+		.UDX(USP_abb2dbb_data),
+		.UEN(USP_enable),
+		.VBATS(VBATS),
+		.VCCS(VCCS),
+		.VCHG(VCHG),
+		.VCK(VSP_clock),
+		.VDR(VSP_DL_data),
+		.VDX(VSP_UL_data),
+		.VFS(VSP_sync),
+		.SIM_IO(SIM_IO),
+		.SIM_CLK(SIM_CLK),
+		.SIM_RST(SIM_RST)
+	);
+
+/* there needs to be a pull-down resistor on the MCUDI/UDX net */
+resistor R216 (USP_abb2dbb_data, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/calypso_179ghh.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,262 @@
+module calypso_179ghh (TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
+			DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
+			VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS,
+			VDDS_RTC, VDD_RTC, VSS_RTC,
+			VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL,
+			SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
+			TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
+			TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
+			MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
+			KBC, KBR, BU_PWT, LT_PWL, GPIO,
+			nRESET_OUT_IO7, nIBOOT, IDDQ,
+			CLKTCXO, VSSO, OSC32K_IN, OSC32K_OUT,
+			CLK32K_OUT, CLK13M_OUT, nRESPWON, EXT_FIQ, EXT_IRQ,
+			TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
+			nEMU, nBSCAN, TDI, TDO, TCK, TMS,
+			BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
+			VDX, VDR, VFSRX, VCLKRX,
+			MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
+			SIM_IO, SIM_CLK, SIM_RST, SIM_CD, SIM_PWCTRL_IO5);
+
+output TSPCLKX, TSPDO;
+inout TSPDI_IO4;
+output [3:0] TSPEN;
+output [11:0] TSPACT;
+
+inout [15:0] DATA;
+output [22:0] ADD;
+output RnW, nFWE, nFOE, FDP, nBLE, nBHE;
+output [4:0] nCS;
+
+input VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS;
+input VDDS_RTC, VDD_RTC, VSS_RTC;
+input VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL;
+
+output SCLK, SDO, nSCS1;
+inout SDI_SDA, nSCS0_SCL;
+
+output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
+input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
+inout DSR_LPG;
+
+output MCSI_TXD;
+input MCSI_RXD;
+inout MCSI_CLK, MCSI_FSYNCH;
+
+output [4:0] KBC;
+input [4:0] KBR;
+output BU_PWT, LT_PWL;
+inout [3:0] GPIO;
+
+output nRESET_OUT_IO7;
+input nIBOOT, IDDQ, CLKTCXO, VSSO;
+inout OSC32K_IN, OSC32K_OUT;
+output CLK32K_OUT, CLK13M_OUT;
+input nRESPWON, EXT_FIQ, EXT_IRQ;
+
+output TCXOEN, RFEN, IT_WAKEUP;
+input ON_OFF;
+
+inout [1:0] nEMU;
+input nBSCAN, TDI, TCK, TMS;
+output TDO;
+
+input BFSR, BDR;
+output BFSX, BDX;
+inout BCLKX_IO6;
+input BCLKR_ARMCLK;
+
+output VDX;
+input VDR, VFSRX, VCLKRX;
+
+input MCUDI;
+output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;
+
+inout SIM_IO, SIM_PWCTRL_IO5;
+output SIM_CLK, SIM_RST;
+input SIM_CD;
+
+/* instantiate the package; the mapping of signals to balls is defined here */
+
+pkg_179GHH pkg (.F3(ADD[0]),
+		.F2(ADD[1]),
+		.G5(ADD[2]),
+		.G4(ADD[3]),
+		.G2(ADD[4]),
+		.G3(ADD[5]),
+		.H1(ADD[6]),
+		.H3(ADD[7]),
+		.H2(ADD[8]),
+		.H4(ADD[9]),
+		.H5(ADD[10]),
+		.J1(ADD[11]),
+		.J2(ADD[12]),
+		.J3(ADD[13]),
+		.J4(ADD[14]),
+		.K3(ADD[15]),
+		.K2(ADD[16]),
+		.K4(ADD[17]),
+		.J5(ADD[18]),
+		.L1(ADD[19]),
+		.L2(ADD[20]),
+		.L3(ADD[21]),
+		.D2(ADD[22]),
+		.B7(DATA[0]),
+		.D7(DATA[1]),
+		.E7(DATA[2]),
+		.D6(DATA[3]),
+		.A6(DATA[4]),
+		.C6(DATA[5]),
+		.E6(DATA[6]),
+		.C5(DATA[7]),
+		.B5(DATA[8]),
+		.D5(DATA[9]),
+		.E5(DATA[10]),
+		.B4(DATA[11]),
+		.C4(DATA[12]),
+		.D4(DATA[13]),
+		.A3(DATA[14]),
+		.B3(DATA[15]),
+		.F4(FDP),
+		.B2(RnW),
+		.F5(nBHE),
+		.E4(nBLE),
+		.C2(nCS[0]),
+		.C3(nCS[1]),
+		.C1(nCS[2]),
+		.D3(nCS[3]),
+		.C11(nCS[4]),
+		.E2(nFOE),
+		.E3(nFWE),
+		.J14(TSPCLKX),
+		.H10(TSPDI_IO4),
+		.H11(TSPDO),
+		.H13(TSPEN[0]),
+		.H12(TSPEN[1]),
+		.H14(TSPEN[2]),
+		.G12(TSPEN[3]),
+		.M12(TSPACT[0]),
+		.M14(TSPACT[1]),
+		.L12(TSPACT[2]),
+		.L13(TSPACT[3]),
+		.J10(TSPACT[4]),
+		.K11(TSPACT[5]),
+		.K13(TSPACT[6]),
+		.K12(TSPACT[7]),
+		.K14(TSPACT[8]),
+		.J11(TSPACT[9]),
+		.J12(TSPACT[10]),
+		.J13(TSPACT[11]),
+		.P9(SCLK),
+		.M9(SDI_SDA),
+		.K8(SDO),
+		.L9(nSCS0_SCL),
+		.N9(nSCS1),
+		.C8(TX_IRDA),
+		.D8(RX_IRDA),
+		.C7(TXIR_IRDA),
+		.A8(RXIR_IRDA),
+		.B8(SD_IRDA),
+		.B9(TX_MODEM),
+		.A9(RX_MODEM),
+		.E8(RTS_MODEM),
+		.D9(DSR_LPG),
+		.C9(CTS_MODEM),
+		.L10(MCSI_TXD),
+		.M10(MCSI_RXD),
+		.N10(MCSI_CLK),
+		.K9(MCSI_FSYNCH),
+		.N4(KBC[0]),
+		.K5(KBC[1]),
+		.L5(KBC[2]),
+		.P5(KBC[3]),
+		.M5(KBC[4]),
+		.K6(KBR[0]),
+		.M6(KBR[1]),
+		.P6(KBR[2]),
+		.N6(KBR[3]),
+		.L6(KBR[4]),
+		.K7(BU_PWT),
+		.L7(LT_PWL),
+		.N3(GPIO[0]),
+		.P3(GPIO[1]),
+		.L4(GPIO[2]),
+		.M4(GPIO[3]),
+		.N2(nRESET_OUT_IO7),
+		.N1(nIBOOT),
+		.M2(IDDQ),
+		.E13(CLKTCXO),
+		.C13(OSC32K_IN),
+		.B13(OSC32K_OUT),
+		.C12(CLK32K_OUT),
+		.F12(CLK13M_OUT),
+		.D12(nRESPWON),
+		.P1(EXT_FIQ),
+		.M3(EXT_IRQ),
+		.A4(VDDS_MIF),
+		.B6(VDDS_MIF),
+		.G1(VDDS_MIF),
+		.D1(VDDS_MIF),
+		.A11(VDDS_2),
+		.L14(VDDS_1),
+		.N5(VDDS_1),
+		.A5(VDD),
+		.B12(VDD),
+		.N14(VDD),
+		.P7(VDD),
+		.M1(VDD),
+		.E1(VDD),
+		.F1(VSS),
+		.N8(VSS),
+		.K1(VSS),
+		.P2(VSS),
+		.P4(VSS),
+		.P10(VSS),
+		.P13(VSS),
+		.G14(VSS),
+		.A10(VSS),
+		.A7(VSS),
+		.A2(VSS),
+		.B1(VSS),
+		.D13(VDDS_RTC),
+		.D14(VDD_RTC),
+		.C14(VSS_RTC),
+		.E11(VDD_ANG),
+		.E12(VSS_ANG),
+		.F11(VDD_PLL),
+		.E14(VSS_PLL),
+		.A14(VSSO),
+		.A12(TCXOEN),
+		.A13(RFEN),
+		.F10(ON_OFF),
+		.B14(IT_WAKEUP),
+		.D11(nBSCAN),
+		.B11(nEMU[0]),
+		.E10(nEMU[1]),
+		.D10(TDI),
+		.C10(TDO),
+		.B10(TCK),
+		.E9(TMS),
+		.L11(BFSR),
+		.K10(BDR),
+		.P12(BFSX),
+		.M11(BDX),
+		.P11(BCLKR_ARMCLK),
+		.N11(BCLKX_IO6),
+		.P14(VDX),
+		.N13(VDR),
+		.M13(VFSRX),
+		.N12(VCLKRX),
+		.N7(MCUDI),
+		.M7(MCUDO),
+		.M8(MCUEN0),
+		.P8(MCUEN1_IO8),
+		.L8(MCUEN2_IO13),
+		.G13(SIM_IO),
+		.F13(SIM_CLK),
+		.G10(SIM_RST),
+		.G11(SIM_CD),
+		.F14(SIM_PWCTRL_IO5)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/clock_rf2dbb.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,12 @@
+module clock_rf2dbb (In, Out);
+
+input In;
+output Out;
+
+wire mid;
+
+resistor R251 (In, mid);
+
+capacitor C253 (mid, Out);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/core.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,231 @@
+/*
+ * This Verilog module encapsulates the Calypso chipset core part
+ * of our Venus development board.
+ */
+
+module core (GND, VBAT1, VBAT2, VBAT3, VSIM, Vio,
+	     PWON, RPWON, nTESTRESET, ON_nOFF,
+	     TDI, TDO, TCK, TMS,
+	     MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE,
+	     EXT_nCS3, EXT_nCS4,
+	     SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
+	     TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
+	     TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
+	     MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
+	     KBC, KBR, BU_PWT, LT_PWL,
+	     GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT,
+	     GPIO8, GPIO13,
+	     ADIN1, ADIN2, ADIN3, DAC,
+	     AUXI, AUXON, AUXOP, EARN, EARP, HSMICBIAS, HSMICP, HSO,
+	     MICBIAS, MICIN, MICIP,
+	     LED_A, LED_B, LED_C,
+	     ICTL, PCHG, VBATS, VCCS, VCHG,
+	     SIM_IO, SIM_CLK, SIM_RST, ANTENNA);
+
+input GND, VBAT1, VBAT2, VBAT3;
+output VSIM, Vio;
+
+input PWON, RPWON, nTESTRESET;
+output ON_nOFF;
+
+input TDI, TCK, TMS;
+output TDO;
+
+output [22:0] MCU_A;
+inout [15:0] MCU_D;
+output MCU_RnW, MCU_nFWE, MCU_nFOE;
+output EXT_nCS3, EXT_nCS4;
+
+output SCLK, SDO, nSCS1;
+inout SDI_SDA, nSCS0_SCL;
+
+output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
+input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
+inout DSR_LPG;
+
+output MCSI_TXD;
+input MCSI_RXD;
+inout MCSI_CLK, MCSI_FSYNCH;
+
+output [4:0] KBC;
+input [4:0] KBR;
+output BU_PWT, LT_PWL;
+
+inout GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, GPIO8, GPIO13;
+
+input ADIN1, ADIN2, ADIN3;
+output DAC;
+
+input AUXI;
+output AUXON, AUXOP;
+output EARN, EARP;
+output HSMICBIAS, HSO;
+input HSMICP;
+output MICBIAS;
+input MICIN, MICIP;
+
+output LED_A, LED_B, LED_C;
+
+output ICTL, PCHG;
+input VBATS, VCCS, VCHG;
+
+output SIM_CLK, SIM_RST;
+inout SIM_IO;
+inout ANTENNA;
+
+/* wires between baseband and RF */
+wire Clock_26MHz_RF_out, Clock_26MHz_DBB_in;
+wire Analog_IM, Analog_IP, Analog_QM, Analog_QP;
+wire AFC, APC;
+wire TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita;
+wire [11:0] TSPACT;
+wire ADIN4;
+
+/* wires between baseband and memory */
+wire Vflash, Vsram;
+wire MCU_FDP, MCU_nBLE, MCU_nBHE;
+wire INT_nCS0, INT_nCS1, INT_nCS2;
+
+/* instantiate the blocks! */
+
+baseband bb (.GND(GND),
+	     .VBAT(VBAT1),
+	     .VSIM(VSIM),
+	     .Vio(Vio),
+	     .Vflash(Vflash),
+	     .Vsram(Vsram),
+	     .PWON(PWON),
+	     .RPWON(RPWON),
+	     .nTESTRESET(nTESTRESET),
+	     .ON_nOFF(ON_nOFF),
+	     .CLKTCXO_IN(Clock_26MHz_DBB_in),
+	     .TDI(TDI),
+	     .TDO(TDO),
+	     .TCK(TCK),
+	     .TMS(TMS),
+	     .MCU_A(MCU_A),
+	     .MCU_D(MCU_D),
+	     .MCU_RnW(MCU_RnW),
+	     .MCU_nFWE(MCU_nFWE),
+	     .MCU_nFOE(MCU_nFOE),
+	     .MCU_FDP(MCU_FDP),
+	     .MCU_nBLE(MCU_nBLE),
+	     .MCU_nBHE(MCU_nBHE),
+	     .MCU_nCS[0](INT_nCS0),
+	     .MCU_nCS[1](INT_nCS1),
+	     .MCU_nCS[2](INT_nCS2),
+	     .MCU_nCS[3](EXT_nCS3),
+	     .MCU_nCS[4](EXT_nCS4),
+	     .SCLK(SCLK),
+	     .SDO(SDO),
+	     .SDI_SDA(SDI_SDA),
+	     .nSCS0_SCL(nSCS0_SCL),
+	     .nSCS1(nSCS1),
+	     .TX_IRDA(TX_IRDA),
+	     .RX_IRDA(RX_IRDA),
+	     .TXIR_IRDA(TXIR_IRDA),
+	     .RXIR_IRDA(RXIR_IRDA),
+	     .SD_IRDA(SD_IRDA),
+	     .TX_MODEM(TX_MODEM),
+	     .RX_MODEM(RX_MODEM),
+	     .RTS_MODEM(RTS_MODEM),
+	     .CTS_MODEM(CTS_MODEM),
+	     .DSR_LPG(DSR_LPG),
+	     .MCSI_TXD(MCSI_TXD),
+	     .MCSI_RXD(MCSI_RXD),
+	     .MCSI_CLK(MCSI_CLK),
+	     .MCSI_FSYNCH(MCSI_FSYNCH),
+	     .KBC(KBC),
+	     .KBR(KBR),
+	     .BU_PWT(BU_PWT),
+	     .LT_PWL(LT_PWL),
+	     .GPIO0(GPIO0),
+	     .GPIO1(GPIO1),
+	     .GPIO2(GPIO2),
+	     .GPIO3(GPIO3),
+	     .GPIO4(GPIO4),
+	     .GPIO6(GPIO6),
+	     .GPIO7_RESETOUT(GPIO7_RESETOUT),
+	     .GPIO8(GPIO8),
+	     .GPIO13(GPIO13),
+	     .ADIN1(ADIN1),
+	     .ADIN2(ADIN2),
+	     .ADIN3(ADIN3),
+	     .ADIN4(ADIN4),
+	     .DAC(DAC),
+	     .AUXI(AUXI),
+	     .AUXON(AUXON),
+	     .AUXOP(AUXOP),
+	     .EARN(EARN),
+	     .EARP(EARP),
+	     .HSMICBIAS(HSMICBIAS),
+	     .HSMICP(HSMICP),
+	     .HSO(HSO),
+	     .MICBIAS(MICBIAS),
+	     .MICIN(MICIN),
+	     .MICIP(MICIP),
+	     .LED_A(LED_A),
+	     .LED_B(LED_B),
+	     .LED_C(LED_C),
+	     .ICTL(ICTL),
+	     .PCHG(PCHG),
+	     .VBATS(VBATS),
+	     .VCCS(VCCS),
+	     .VCHG(VCHG),
+	     .SIM_IO(SIM_IO),
+	     .SIM_CLK(SIM_CLK),
+	     .SIM_RST(SIM_RST),
+	     .Analog_IM(Analog_IM),
+	     .Analog_IP(Analog_IP),
+	     .Analog_QM(Analog_QM),
+	     .Analog_QP(Analog_QP),
+	     .AFC(AFC),
+	     .APC(APC),
+	     .TCXOEN(TCXOEN),
+	     .RFEN(RFEN),
+	     .TSPCLK(TSPCLK),
+	     .TSPDO(TSPDO),
+	     .TSPEN_Rita(TSPEN_Rita),
+	     .TSPACT(TSPACT)
+	);
+
+memory mem (.GND(GND),
+	    .Vflash(Vflash),
+	    .Vsram(Vsram),
+	    .MCU_A(MCU_A[22:1]),
+	    .MCU_D(MCU_D[15:0]),
+	    .MCU_nRD(MCU_nFOE),
+	    .MCU_nWR(MCU_RnW),
+	    .MCU_nBHE(MCU_nBHE),
+	    .MCU_nBLE(MCU_nBLE),
+	    .Flash_RST(MCU_FDP),
+	    .CS_flash1(INT_nCS0),
+	    .CS_RAM(INT_nCS1)
+	);
+
+rf_section rf  (.GND(GND),
+		.VBAT_REG(VBAT2),
+		.VBAT_PA(VBAT3),
+		.Vio(Vio),
+		.Analog_IM(Analog_IM),
+		.Analog_IP(Analog_IP),
+		.Analog_QM(Analog_QM),
+		.Analog_QP(Analog_QP),
+		.AFC(AFC),
+		.APC(APC),
+		.TCXOEN(TCXOEN),
+		.RFEN(RFEN),
+		.TSPCLK(TSPCLK),
+		.TSPDO(TSPDO),
+		.TSPEN_Rita(TSPEN_Rita),
+		.TSPACT(TSPACT),
+		.Clock_out_to_DBB(Clock_26MHz_RF_out),
+		.RTEMP_VTEST(ADIN4),
+		.ANTENNA(ANTENNA)
+	);
+
+clock_rf2dbb clock_rf2dbb (.In(Clock_26MHz_RF_out),
+			   .Out(Clock_26MHz_DBB_in)
+		);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/dbb_block.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,212 @@
+/*
+ * This module encapsulates the Calypso DBB chip plus the following:
+ *
+ * - star points and bypass capacitors for the powering arrangement;
+ * - the 32 kHz xtal circuit with its special ground;
+ * - nIBOOT, IDDQ, SIM_CD and SIM_PWCTRL tie-offs;
+ * - nBSCAN and nEMU[1:0] no-connects.
+ *
+ * All other Calypso signals are passed through untouched.
+ */
+
+module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc,
+		  TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
+		  DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
+		  SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
+		  TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
+		  TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
+		  MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
+		  KBC, KBR, BU_PWT, LT_PWL, GPIO,
+		  nRESET_OUT_IO7, CLKTCXO,
+		  CLK32K_OUT, CLK13M_OUT, nRESPWON, EXT_FIQ, EXT_IRQ,
+		  TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
+		  TDI, TDO, TCK, TMS,
+		  BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
+		  VDX, VDR, VFSRX, VCLKRX,
+		  MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
+		  SIM_IO, SIM_CLK, SIM_RST);
+
+input GND, Vdbb, Vio, Vflash, Vrtc;
+
+output TSPCLKX, TSPDO;
+inout TSPDI_IO4;
+output [3:0] TSPEN;
+output [11:0] TSPACT;
+
+inout [15:0] DATA;
+output [22:0] ADD;
+output RnW, nFWE, nFOE, FDP, nBLE, nBHE;
+output [4:0] nCS;
+
+output SCLK, SDO, nSCS1;
+inout SDI_SDA, nSCS0_SCL;
+
+output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
+input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
+inout DSR_LPG;
+
+output MCSI_TXD;
+input MCSI_RXD;
+inout MCSI_CLK, MCSI_FSYNCH;
+
+output [4:0] KBC;
+input [4:0] KBR;
+output BU_PWT, LT_PWL;
+inout [3:0] GPIO;
+
+output nRESET_OUT_IO7;
+input CLKTCXO;
+output CLK32K_OUT, CLK13M_OUT;
+input nRESPWON, EXT_FIQ, EXT_IRQ;
+
+output TCXOEN, RFEN, IT_WAKEUP;
+input ON_OFF;
+
+input TDI, TCK, TMS;
+output TDO;
+
+input BFSR, BDR;
+output BFSX, BDX;
+inout BCLKX_IO6;
+input BCLKR_ARMCLK;
+
+output VDX;
+input VDR, VFSRX, VCLKRX;
+
+input MCUDI;
+output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;
+
+inout SIM_IO;
+output SIM_CLK, SIM_RST;
+
+/* nets inside this module */
+wire SIM_PWCTRL;
+wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2;
+wire VDD_PLL, VDD_CORE;
+
+starpoint HST201 (Vdbb, VDD_PLL);
+starpoint HST202 (Vdbb, VDD_CORE);
+
+/* instantiate the Calypso! */
+
+calypso_179ghh calypso (.TSPCLKX(TSPCLKX),
+			.TSPDO(TSPDO),
+			.TSPDI_IO4(TSPDI_IO4),
+			.TSPEN(TSPEN),
+			.TSPACT(TSPACT),
+			.DATA(DATA),
+			.ADD(ADD),
+			.RnW(RnW),
+			.nFWE(nFWE),
+			.nFOE(nFOE),
+			.FDP(FDP),
+			.nBLE(nBLE),
+			.nBHE(nBHE),
+			.nCS(nCS),
+			.VDDS_MIF(Vflash),
+			.VDDS_1(Vio),
+			.VDDS_2(Vio),
+			.VDD(VDD_CORE),
+			.VSS(GND),
+			.VDDS_RTC(Vrtc),
+			.VDD_RTC(Vrtc),
+			.VSS_RTC(GND),
+			.VDD_ANG(Vio),
+			.VSS_ANG(GND),
+			.VDD_PLL(VDD_PLL),
+			.VSS_PLL(GND),
+			.SCLK(SCLK),
+			.SDO(SDO),
+			.SDI_SDA(SDI_SDA),
+			.nSCS0_SCL(nSCS0_SCL),
+			.nSCS1(nSCS1),
+			.TX_IRDA(TX_IRDA),
+			.RX_IRDA(RX_IRDA),
+			.TXIR_IRDA(TXIR_IRDA),
+			.RXIR_IRDA(RXIR_IRDA),
+			.SD_IRDA(SD_IRDA),
+			.TX_MODEM(TX_MODEM),
+			.RX_MODEM(RX_MODEM),
+			.RTS_MODEM(RTS_MODEM),
+			.CTS_MODEM(CTS_MODEM),
+			.DSR_LPG(DSR_LPG),
+			.MCSI_TXD(MCSI_TXD),
+			.MCSI_RXD(MCSI_RXD),
+			.MCSI_CLK(MCSI_CLK),
+			.MCSI_FSYNCH(MCSI_FSYNCH),
+			.KBC(KBC),
+			.KBR(KBR),
+			.BU_PWT(BU_PWT),
+			.LT_PWL(LT_PWL),
+			.GPIO(GPIO),
+			.nRESET_OUT_IO7(nRESET_OUT_IO7),
+			.nIBOOT(GND),
+			.IDDQ(GND),
+			.CLKTCXO(CLKTCXO),
+			.VSSO(GND_32khz),
+			.OSC32K_IN(OSC32K_IN),
+			.OSC32K_OUT(OSC32K_OUT),
+			.CLK32K_OUT(CLK32K_OUT),
+			.CLK13M_OUT(CLK13M_OUT),
+			.nRESPWON(nRESPWON),
+			.EXT_FIQ(EXT_FIQ),
+			.EXT_IRQ(EXT_IRQ),
+			.TCXOEN(TCXOEN),
+			.RFEN(RFEN),
+			.ON_OFF(ON_OFF),
+			.IT_WAKEUP(IT_WAKEUP),
+			.nEMU(),	/* no connect */
+			.nBSCAN(),	/* ditto */
+			.TDI(TDI),
+			.TDO(TDO),
+			.TCK(TCK),
+			.TMS(TMS),
+			.BFSR(BFSR),
+			.BDR(BDR),
+			.BFSX(BFSX),
+			.BDX(BDX),
+			.BCLKX_IO6(BCLKX_IO6),
+			.BCLKR_ARMCLK(BCLKR_ARMCLK),
+			.VDX(VDX),
+			.VDR(VDR),
+			.VFSRX(VFSRX),
+			.VCLKRX(VCLKRX),
+			.MCUDI(MCUDI),
+			.MCUDO(MCUDO),
+			.MCUEN0(MCUEN0),
+			.MCUEN1_IO8(MCUEN1_IO8),
+			.MCUEN2_IO13(MCUEN2_IO13),
+			.SIM_IO(SIM_IO),
+			.SIM_CLK(SIM_CLK),
+			.SIM_RST(SIM_RST),
+			.SIM_CD(Vio),
+			.SIM_PWCTRL_IO5(SIM_PWCTRL));
+
+/* power bypass caps, absolutely unchanged from Leonardo */
+
+capacitor C209 (Vflash, GND);
+capacitor C210 (Vio, GND);
+capacitor C211 (VDD_CORE, GND);
+capacitor C212 (VDD_PLL, GND);
+
+/* 32.768 kHz xtal circuit, following Leonardo schematics */
+
+/* special ground */
+starpoint HST203 (GND, GND_32khz);
+
+/* resistor and extra cap on OSC32K_OUT */
+resistor R215 (OSC32K_OUT, OSC32K_OUT_2);
+capacitor C223 (OSC32K_OUT, GND);	/* regular GND per Leonardo schem */
+
+/* actual xtal and caps */
+xtal_32khz_wrap xtal (OSC32K_IN, OSC32K_OUT_2, GND);	/* pkg case GND */
+capacitor C202 (OSC32K_IN, GND_32khz);
+capacitor C203 (OSC32K_OUT_2, GND_32khz);
+
+/* Vrtc bypass cap */
+capacitor C201 (Vrtc, GND_32khz);
+
+/* SIM_PWCTRL resistor like on Leonardo schematics */
+resistor R207 (SIM_PWCTRL, SIM_IO);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/int_vcxo_passive.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,28 @@
+/*
+ * This module captures the mysterious all-passive circuit between Iota's
+ * AFC output and Rita's XIN input as depicted on the Leonardo schematics.
+ * This circuit defies understanding, but it appears in Openmoko's GSM
+ * modem (unchanged from Leonardo) and that modem works, hence we deem
+ * this voodoo circuit to be suitable for mindless copying w/o understanding...
+ *
+ * Note that C205 is not included here, as it's already been included
+ * in the abb_block wrapper instead.
+ */
+
+module int_vcxo_passive (AFC_in, XIN_connection, GND);
+
+input AFC_in, GND;
+inout XIN_connection;
+
+wire R217_to_xtal, xtal_to_R211, R211_to_C225;
+
+resistor R217 (AFC_in, R217_to_xtal);
+varactor_diode D200 (.Cathode(R217_to_xtal), .Anode(GND));
+capacitor C226 (R217_to_xtal, GND);
+xtal_4pin_pkg xtal (.pin_1(xtal_to_R211), .pin_2(GND),
+		    .pin_3(R217_to_xtal), .pin_4(GND));
+resistor R211 (xtal_to_R211, R211_to_C225);
+capacitor C224 (R211_to_C225, GND);
+capacitor C225 (R211_to_C225, XIN_connection);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/iota_100ggm.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,175 @@
+module iota_100ggm (ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
+		    BDLIM, BDLIP, BDLQM, BDLQP, BDR, BDX, BFSR, BFSX, BULIM,
+		    BULIP, BULQM, BULQP, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
+		    DBBSRST, EARN, EARP, GNDA, GNDAV, GNDD, GNDL1, GNDL2,
+		    HSMICBIAS, HSMICP, HSO, IBIAS, ICTL, INT1, INT2, ITWAKEUP,
+		    LEDA, LEDB1, LEDB2, LEDC, MICBIAS, MICIN, MICIP, ON_nOFF,
+		    PCHG, PWON, REFGND, RESPWONz, RPWON, SIMCK, SIMIO, SIMRST,
+		    TCK, TDI, TDO, TDR, TEN, TEST3, TEST4, TESTRSTz, TESTV,
+		    TMS, UDR, UDX, UEN, UPR, VBACKUP, VBAT, VBATS, VCABB, VCCS,
+		    VCDBB, VCHG, VCIO1, VCIO2, VCK, VCMEM, VCRAM, VDR, VDX,
+		    VFS, VLMEM, VLRTC, VRABB, VRDBB, VREF, VRIO1, VRIO2, VRMEM,
+		    VRRAM, VRRTC, VRSIM, VSDBB, VXRTC);
+
+input ADIN1, ADIN2, ADIN3, ADIN4;
+output AFC, APC, DAC;
+
+input AUXI;
+output AUXON, AUXOP;
+output EARN, EARP;
+output HSMICBIAS, HSO;
+input HSMICP;
+output MICBIAS;
+input MICIN, MICIP;
+
+input BDLIM, BDLIP, BDLQM, BDLQP;
+output BULIM, BULIP, BULQM, BULQP;
+
+input BDR, BFSR;
+output BDX, BFSX;
+input TDR, TEN;
+input UDR, UEN;
+output UDX;
+output VCK, VDX, VFS;
+input VDR;
+
+input CK13M, CK32K, ITWAKEUP;
+output INT1, INT2;
+output ON_nOFF, RESPWONz;
+
+input DBBSCK, DBBSRST;
+inout DBBSIO;
+
+input GNDA, GNDAV, GNDD, GNDL1, GNDL2;
+
+inout IBIAS, VREF, REFGND;
+
+input PWON, RPWON;
+output ICTL, PCHG;
+
+output LEDA, LEDB1, LEDB2, LEDC;
+
+output SIMCK, SIMRST;
+inout SIMIO;
+
+input TCK, TDI, TMS;
+output TDO;
+inout TEST3, TEST4;
+input TESTRSTz;
+output TESTV;
+
+inout UPR;
+input VBACKUP, VBAT, VBATS, VCABB, VCCS, VCDBB, VCHG, VCIO1, VCIO2;
+input VCMEM, VCRAM;
+
+input VLMEM, VLRTC;
+output VRABB, VRDBB, VRIO1, VRIO2, VRMEM, VRRAM, VRRTC, VRSIM;
+
+input VSDBB;
+inout VXRTC;
+
+/* instantiate the package; the mapping of signals to balls is defined here */
+
+pkg_100GGM pkg (.B6(ADIN1),
+		.A6(ADIN2),
+		.C7(ADIN3),
+		.C6(ADIN4),
+		.J4(AFC),
+		.K4(APC),
+		.G7(AUXI),
+		.K10(AUXON),
+		.K9(AUXOP),
+		.F10(BDLIM),
+		.F9(BDLIP),
+		.E9(BDLQM),
+		.E10(BDLQP),
+		.J3(BDR),
+		.J2(BDX),
+		.H3(BFSR),
+		.K2(BFSX),
+		.D10(BULIM),
+		.D9(BULIP),
+		.C9(BULQM),
+		.C10(BULQP),
+		.E4(CK13M),
+		.E2(CK32K),
+		.H4(DAC),
+		.F4(DBBSCK),
+		.E5(DBBSIO),
+		.G4(DBBSRST),
+		.J10(EARN),
+		.J9(EARP),
+		.G10(GNDA),
+		.G6(GNDAV),
+		.A3(GNDD),
+		.B9(GNDL1),
+		.A9(GNDL2),
+		.K8(HSMICBIAS),
+		.K7(HSMICP),
+		.H9(HSO),
+		.B7(IBIAS),
+		.D6(ICTL),
+		.H6(INT1),
+		.E6(INT2),
+		.D2(ITWAKEUP),
+		.B8(LEDA),
+		.B10(LEDB1),
+		.A10(LEDB2),
+		.C8(LEDC),
+		.J8(MICBIAS),
+		.H7(MICIN),
+		.J7(MICIP),
+		.E3(ON_nOFF),
+		.B5(PCHG),
+		.F8(PWON),
+		.A7(REFGND),
+		.D3(RESPWONz),
+		.F7(RPWON),
+		.C4(SIMCK),
+		.B3(SIMIO),
+		.D4(SIMRST),
+		.D8(TCK),
+		.D7(TDI),
+		.E7(TDO),
+		.G3(TDR),
+		.H1(TEN),
+		.J6(TEST3),
+		.F6(TEST4),
+		.H8(TESTRSTz),
+		.G8(TESTV),
+		.E8(TMS),
+		.K5(UDR),
+		.J5(UDX),
+		.K6(UEN),
+		.C2(UPR),
+		.E1(VBACKUP),
+		.A4(VBAT),
+		.C5(VBATS),
+		.G9(VCABB),
+		.D5(VCCS),
+		.K1(VCDBB),
+		.A5(VCHG),
+		.A2(VCIO1),
+		.A1(VCIO2),
+		.K3(VCK),
+		.G2(VCMEM),
+		.F2(VCRAM),
+		.F5(VDR),
+		.H5(VDX),
+		.G5(VFS),
+		.F3(VLMEM),
+		.C3(VLRTC),
+		.H10(VRABB),
+		.J1(VRDBB),
+		.A8(VREF),
+		.B2(VRIO1),
+		.B1(VRIO2),
+		.G1(VRMEM),
+		.F1(VRRAM),
+		.D1(VRRTC),
+		.B4(VRSIM),
+		.H2(VSDBB),
+		.C1(VXRTC)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/memory.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,33 @@
+module memory  (GND, Vflash, Vsram,
+		MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE,
+		Flash_RST, CS_flash1, CS_RAM);
+
+input GND, Vflash, Vsram;
+input [22:1] MCU_A;
+inout [15:0] MCU_D;
+input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE;
+input Flash_RST;
+input CS_flash1, CS_RAM;
+
+S71PL064J chip (.Flash_Vcc(Vflash),
+		.RAM_Vcc(Vsram),
+		.Vss(GND),
+		.A(MCU_A),
+		.DQ(MCU_D),
+		.OE(MCU_nRD),
+		.WE(MCU_nWR),
+		.Flash_CE1(CS_flash1),
+		.Flash_RST(Flash_RST),
+		.Flash_WP_ACC(Vflash),
+		.Flash_ready_busy(),	/* no connect */
+		.RAM_CE_actlow(CS_RAM),
+		.RAM_CE_acthigh(Vsram),
+		.RAM_UB(MCU_nBHE),
+		.RAM_LB(MCU_nBLE)
+	);
+
+/* bypass caps */
+capacitor C318 (Vsram, GND);
+capacitor C322 (Vflash, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rf_fem_block.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,50 @@
+/*
+ * This module encapsulates the RF FEM (quadband M034F) along with the PNP
+ * transistors and R/C footprints to GND for the control lines, and the cap
+ * on the antenna output.
+ */
+
+module rf_fem_block (GND, VREG3, Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850,
+		     RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
+		     TX_LOW, TX_HIGH, ANT);
+
+input GND, VREG3;
+input Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850;
+
+output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
+input TX_LOW, TX_HIGH;
+inout ANT;
+
+wire ANT_before_cap;
+wire V_TX_LOW, V_TX_HIGH, V_RX_850;
+
+/* transform control signals through PNP transistors */
+
+transistor_slot PNP_FEM7 (.E(VREG3), .B(Ctrl_Tx_Low), .C(V_TX_LOW));
+transistor_slot PNP_FEM8 (.E(VREG3), .B(Ctrl_Tx_High), .C(V_TX_HIGH));
+transistor_slot PNP_FEM9 (.E(VREG3), .B(Ctrl_Rx_850), .C(V_RX_850));
+
+/* instantiate the M034F */
+
+M034F M034F (.ANT(ANT_before_cap),
+	     .GND(GND),
+	     .RX_LOW1(RX_LOW1),
+	     .RX_LOW2(RX_LOW2),
+	     .RX_DCS1(RX_DCS1),
+	     .RX_DCS2(RX_DCS2),
+	     .RX_PCS1(RX_PCS1),
+	     .RX_PCS2(RX_PCS2),
+	     .TX_LOW(TX_LOW),
+	     .TX_HIGH(TX_HIGH),
+	     .V_TX_LOW(V_TX_LOW),
+	     .V_TX_HIGH(V_TX_HIGH),
+	     .V_RX_850(V_RX_850)
+	);
+
+capacitor C635 (ANT_before_cap, ANT);
+
+capacitor C645 (V_TX_LOW, GND);
+capacitor C644 (V_TX_HIGH, GND);
+capacitor C643 (V_RX_850, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rf_pa_block.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,46 @@
+/*
+ * This module encapsulates the RF PA along with its power bypass caps
+ * and the Rs and Cs on the control inputs.
+ */
+
+module rf_pa_block (GND, VBAT, Band_Select, Tx_Enable, APC_in,
+			LB_RF_in, HB_RF_in, LB_RF_out, HB_RF_out);
+
+input GND, VBAT;
+input Band_Select, Tx_Enable, APC_in;
+input LB_RF_in, HB_RF_in;
+output LB_RF_out, HB_RF_out;
+
+/*
+ * A little bit of muck with the control inputs, following Leonardo
+ * and Openmoko schematics.  On FC Venus we completely eliminate
+ * R621 and R622.
+ */
+
+wire APC_after_resistor;
+
+resistor R623 (APC_in, APC_after_resistor);
+capacitor C648 (APC_after_resistor, GND);
+capacitor C656 (Band_Select, GND);
+
+/* instantiate the PA itself */
+
+RF3166 PA (.HB_RF_in(HB_RF_in),
+	   .Band_Select(Band_Select),
+	   .Tx_Enable(Tx_Enable),
+	   .Vbatt(VBAT),
+	   .GND(GND),
+	   .Vramp(APC_after_resistor),
+	   .LB_RF_in(LB_RF_in),
+	   .LB_RF_out(LB_RF_out),
+	   .HB_RF_out(HB_RF_out)
+	);
+
+/* 4 bypass caps per both Leonardo and Openmoko schematics */
+
+capacitor C651 (VBAT, GND);
+capacitor C652 (VBAT, GND);
+capacitor C653 (VBAT, GND);
+capacitor C654 (VBAT, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rf_section.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,115 @@
+module rf_section (GND, VBAT_REG, VBAT_PA, Vio,
+		   Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC,
+		   TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT,
+		   Clock_out_to_DBB, RTEMP_VTEST, ANTENNA);
+
+input GND, VBAT_REG, VBAT_PA, Vio;
+
+inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
+input AFC, APC;
+input TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita;
+input [11:0] TSPACT;
+
+output Clock_out_to_DBB, RTEMP_VTEST;
+inout ANTENNA;
+
+/* wires between subblocks */
+wire VREG3;
+wire LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
+wire Rita_LBTXOUT, Rita_HBTXOUT;
+wire PA_LB_in, PA_HB_in, PA_LB_out, PA_HB_out;
+wire FEM_TX_LB_in, FEM_TX_HB_in;
+wire FEMout_to_LNAGSMN, FEMout_to_LNAGSMP;
+wire FEMout_to_LNADCSN, FEMout_to_LNADCSP;
+wire FEMout_to_LNAPCSN, FEMout_to_LNAPCSP;
+
+/* instantiate the main subblocks */
+
+rita_vcxo_int Rita_vcxo (.GND(GND),
+			 .VBAT(VBAT_REG),
+			 .VREG3(VREG3),
+			 .VRIO(Vio),
+			 .TCXOEN(TCXOEN),
+			 .RFEN(RFEN),
+			 .AFC_in(AFC),
+			 .Clock_out_to_DBB(Clock_out_to_DBB),
+			 .Ctrl_CLK(TSPCLK),
+			 .Ctrl_DATA(TSPDO),
+			 .Ctrl_STROBE(TSPEN_Rita),
+			 .Ctrl_RESETZ(TSPACT[0]),
+			 .IN(Analog_IM),
+			 .IP(Analog_IP),
+			 .QN(Analog_QM),
+			 .QP(Analog_QP),
+			 .LNAGSMN(LNAGSMN),
+			 .LNAGSMP(LNAGSMP),
+			 .LNADCSN(LNADCSN),
+			 .LNADCSP(LNADCSP),
+			 .LNAPCSN(LNAPCSN),
+			 .LNAPCSP(LNAPCSP),
+			 .LBTXOUT(Rita_LBTXOUT),
+			 .HBTXOUT(Rita_HBTXOUT),
+			 .DAC(GND),
+			 .DET1(GND),
+			 .DET2(GND),
+			 .APC(),		/* no connect */
+			 .RTEMP_VTEST(RTEMP_VTEST)
+	);
+
+rf_pa_block PA (.GND(GND),
+		.VBAT(VBAT_PA),
+		.Band_Select(TSPACT[3]),
+		.Tx_Enable(TSPACT[9]),
+		.APC_in(APC),
+		.LB_RF_in(PA_LB_in),
+		.HB_RF_in(PA_HB_in),
+		.LB_RF_out(PA_LB_out),
+		.HB_RF_out(PA_HB_out)
+	);
+
+rf_fem_block FEM (.GND(GND),
+		  .VREG3(VREG3),
+		  .Ctrl_Tx_Low(TSPACT[2]),
+		  .Ctrl_Tx_High(TSPACT[1]),
+		  .Ctrl_Rx_850(TSPACT[4]),
+		  .RX_LOW1(FEMout_to_LNAGSMP),
+		  .RX_LOW2(FEMout_to_LNAGSMN),
+		  .RX_DCS1(FEMout_to_LNADCSN),
+		  .RX_DCS2(FEMout_to_LNADCSP),
+		  .RX_PCS1(FEMout_to_LNAPCSN),
+		  .RX_PCS2(FEMout_to_LNAPCSP),
+		  .TX_LOW(FEM_TX_LB_in),
+		  .TX_HIGH(FEM_TX_HB_in),
+		  .ANT(ANTENNA)
+	);
+
+/* RF magic glue connecting the blocks */
+
+/* Tx: Rita to PA */
+rfmatch_rita2pa_lb rita2pa_lb (.In(Rita_LBTXOUT), .Out(PA_LB_in), .GND(GND));
+rfmatch_rita2pa_hb rita2pa_hb (.In(Rita_HBTXOUT), .Out(PA_HB_in), .GND(GND),
+				.VREG3(VREG3));
+
+/* Tx: PA to FEM */
+rfmatch_pa2fem_pi pa2fem_lb (.In(PA_LB_out), .Out(FEM_TX_LB_in), .GND(GND));
+rfmatch_pa2fem_pi pa2fem_hb (.In(PA_HB_out), .Out(FEM_TX_HB_in), .GND(GND));
+
+/* Rx paths (3) from the FEM to Rita LNA inputs */
+
+rfmatch_fem2rita_low fem2rita_low (.In_neg(FEMout_to_LNAGSMN),
+				   .In_pos(FEMout_to_LNAGSMP),
+				   .Out_neg(LNAGSMN),
+				   .Out_pos(LNAGSMP)
+			);
+rfmatch_fem2rita_dcs fem2rita_dcs (.In_neg(FEMout_to_LNADCSN),
+				   .In_pos(FEMout_to_LNADCSP),
+				   .Out_neg(LNADCSN),
+				   .Out_pos(LNADCSP)
+			);
+rfmatch_fem2rita_pcs fem2rita_pcs (.In_neg(FEMout_to_LNAPCSN),
+				   .In_pos(FEMout_to_LNAPCSP),
+				   .Out_neg(LNAPCSN),
+				   .Out_pos(LNAPCSP)
+			);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_fem2rita_dcs.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,13 @@
+/* RF Rx path from quadband FEM to Rita, DCS band, per Leonardo schematics */
+
+module rfmatch_fem2rita_dcs (In_neg, In_pos, Out_neg, Out_pos);
+
+input In_neg, In_pos;
+output Out_neg, Out_pos;
+
+inductor L607 (In_neg, Out_neg);
+inductor L608 (In_pos, Out_pos);
+
+capacitor C699 (Out_neg, Out_pos);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_fem2rita_low.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,16 @@
+/* RF Rx path from quadband FEM to Rita, low bands, per Leonardo schematics */
+
+module rfmatch_fem2rita_low (In_neg, In_pos, Out_neg, Out_pos);
+
+input In_neg, In_pos;
+output Out_neg, Out_pos;
+
+wire mid_neg, mid_pos;
+
+capacitor C614 (In_neg, mid_neg);
+capacitor C615 (In_pos, mid_pos);
+
+inductor L605 (mid_neg, Out_neg);
+inductor L606 (mid_pos, Out_pos);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_fem2rita_pcs.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,13 @@
+/* RF Rx path from quadband FEM to Rita, PCS band, per Leonardo schematics */
+
+module rfmatch_fem2rita_pcs (In_neg, In_pos, Out_neg, Out_pos);
+
+input In_neg, In_pos;
+output Out_neg, Out_pos;
+
+inductor L604 (In_neg, In_pos);
+
+capacitor C624 (In_neg, Out_neg);
+capacitor C625 (In_pos, Out_pos);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_pa2fem_pi.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,14 @@
+/* RF Tx path from PA to M034F FEM, replicated for high and low bands */
+/* we are going to use a generic pi network topology on FC Venus */
+
+module rfmatch_pa2fem_pi (In, Out, GND);
+
+input In;
+output Out;
+input GND;
+
+rlc_generic series (In, Out);
+rlc_generic GND_leg_in (In, GND);
+rlc_generic GND_leg_out (Out, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_rita2pa_hb.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,15 @@
+/* RF Tx path from Rita to PA, high bands */
+
+module rfmatch_rita2pa_hb (In, Out, GND, VREG3);
+
+input In;
+output Out;
+input GND, VREG3;
+
+wire mid;
+
+inductor L600 (In, VREG3);
+capacitor C600 (In, mid);
+chip_attenuator R601 (mid, Out, GND, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rfmatch_rita2pa_lb.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,15 @@
+/* RF Tx path from Rita to PA, low bands */
+
+module rfmatch_rita2pa_lb (In, Out, GND);
+
+input In;
+output Out;
+input GND;
+
+wire mid1, mid2;
+
+inductor L601 (In, mid1);
+capacitor C655 (mid1, mid2);
+chip_attenuator R600 (mid2, Out, GND, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rita_rf_chip.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,87 @@
+module rita_rf_chip (GND,
+		     CLK, DATA, STROBE, RESETZ,
+		     IN, IP, QN, QP,
+		     LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
+		     LBTXOUT, HBTXOUT,
+		     DAC, DET1, DET2, APC,
+		     RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2,
+		     VBAT1, VBAT2, VREG1, VREG2, VREG3, VRIO,
+		     VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9,
+		     VCC10, VCC11, VCC12, VCC13, VBG,
+		     XEN, XSEL, XIN, XOUT);
+
+input GND;
+input CLK, DATA, STROBE, RESETZ;
+inout IN, IP, QN, QP;
+
+input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
+output LBTXOUT, HBTXOUT;
+
+input DAC, DET1, DET2;
+output APC;
+
+output RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2;
+
+input VBAT1, VBAT2, VRIO;
+output VREG1, VREG2, VREG3;
+inout VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9;
+inout VCC10, VCC11, VCC12, VCC13, VBG;
+
+input XEN, XSEL;
+inout XIN;
+output XOUT;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_Rita_RF pkg (.pin_1(XSEL),
+		 .pin_2(XEN),
+		 .pin_3(RESETZ),
+		 .pin_4(VCC1),
+		 .pin_5(DATA),
+		 .pin_6(VCC2),
+		 .pin_7(CLK),
+		 .pin_8(VCC3),
+		 .pin_9(STROBE),
+		.pin_10(VCC4),
+		.pin_11(VCC5),
+		.pin_12(VCC6),
+		.pin_13(SIOUT_TST),
+		.pin_14(RTEMP_VTEST),
+		.pin_15(LNAPCSP),
+		.pin_16(LNAPCSN),
+		.pin_17(VCC7),
+		.pin_18(LNADCSP),
+		.pin_19(LNADCSN),
+		.pin_20(VBG),
+		.pin_21(LNAGSMP),
+		.pin_22(LNAGSMN),
+		.pin_23(VREG3),
+		.pin_24(VBAT2),
+		.pin_25(DET1),
+		.pin_26(DET2),
+		.pin_27(APC),
+		.pin_28(DAC),
+		.pin_29(HBTXOUT),
+		.pin_30(VCC8),
+		.pin_31(LBTXOUT),
+		.pin_32(VCC9),
+		.pin_33(VCC10),
+		.pin_34(TSTVCO1),
+		.pin_35(TSTVCO2),
+		.pin_36(VCC11),
+		.pin_37(VCC12),
+		.pin_38(IN),
+		.pin_39(IP),
+		.pin_40(QP),
+		.pin_41(QN),
+		.pin_42(VCC13),
+		.pin_43(VREG1),
+		.pin_44(VBAT1),
+		.pin_45(VREG2),
+		.pin_46(VRIO),
+		.pin_47(XOUT),
+		.pin_48(XIN),
+		.pin_49(GND)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rita_vcxo_int.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,85 @@
+/*
+ * This module encapsulates the Rita block (Rita chip + caps) together with
+ * the choice of internal or external VC(TC)XO; this version is for the
+ * internal configuration.
+ */
+
+module rita_vcxo_int (GND, VBAT, VREG3, VRIO,
+		      TCXOEN, RFEN, AFC_in, Clock_out_to_DBB,
+		      Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
+		      IN, IP, QN, QP,
+		      LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
+		      LBTXOUT, HBTXOUT,
+		      DAC, DET1, DET2, APC,
+		      RTEMP_VTEST);
+
+input GND, VBAT, VRIO;
+output VREG3;
+
+input TCXOEN, RFEN, AFC_in;
+output Clock_out_to_DBB;
+
+input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
+inout IN, IP, QN, QP;
+
+input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
+output LBTXOUT, HBTXOUT;
+
+input DAC, DET1, DET2;
+output APC;
+
+output RTEMP_VTEST;
+
+/* internal VCTCXO configuration */
+
+wire XIN;
+
+int_vcxo_passive vcxo_passive (AFC_in, XIN, GND);
+
+/*
+ * Some Leonardo schematic versions show a "resistor short" with refdes R604
+ * between TCXOEN from the Calypso and the net going to XEN, XSEL and the cap
+ * or two caps.  In Openmoko's version this component is a physical 0402 SMT
+ * 0R jumper; in iWOW TR-800 this series R has been measured to be 47 Ohm
+ * instead.  On FC Venus we shall include an 0402 series R footprint
+ * just in case.
+ */
+
+wire TCXOEN_after_0R;
+
+resistor R604 (TCXOEN, TCXOEN_after_0R);
+
+/* instantiate the Rita block */
+
+rita_wrap rita (.GND(GND),
+		.VBAT(VBAT),
+		.VREG3(VREG3),
+		.VRIO(VRIO),
+		.XEN(TCXOEN_after_0R),
+		.XSEL(TCXOEN_after_0R),
+		.XIN(XIN),
+		.Clock_out_to_DBB(Clock_out_to_DBB),
+		.Ctrl_CLK(Ctrl_CLK),
+		.Ctrl_DATA(Ctrl_DATA),
+		.Ctrl_STROBE(Ctrl_STROBE),
+		.Ctrl_RESETZ(Ctrl_RESETZ),
+		.IN(IN),
+		.IP(IP),
+		.QN(QN),
+		.QP(QP),
+		.LNAGSMN(LNAGSMN),
+		.LNAGSMP(LNAGSMP),
+		.LNADCSN(LNADCSN),
+		.LNADCSP(LNADCSP),
+		.LNAPCSN(LNAPCSN),
+		.LNAPCSP(LNAPCSP),
+		.LBTXOUT(LBTXOUT),
+		.HBTXOUT(HBTXOUT),
+		.DAC(DAC),
+		.DET1(DET1),
+		.DET2(DET2),
+		.APC(APC),
+		.RTEMP_VTEST(RTEMP_VTEST)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/rita_wrap.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,118 @@
+/*
+ * This module encapsulates the Rita chip along with the surrounding entourage
+ * of power bypass capacitors; all other Rita signals are passed through
+ * unchanged.
+ */
+
+module rita_wrap (GND, VBAT, VREG3, VRIO,
+		  XEN, XSEL, XIN, Clock_out_to_DBB,
+		  Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
+		  IN, IP, QN, QP,
+		  LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
+		  LBTXOUT, HBTXOUT,
+		  DAC, DET1, DET2, APC,
+		  RTEMP_VTEST);
+
+input GND, VBAT, VRIO;
+output VREG3;
+
+input XEN, XSEL, XIN;
+output Clock_out_to_DBB;
+
+input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
+inout IN, IP, QN, QP;
+
+input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
+output LBTXOUT, HBTXOUT;
+
+input DAC, DET1, DET2;
+output APC;
+
+output RTEMP_VTEST;
+
+/* Rita power nets contained inside this wrapper */
+
+wire VREG1, VREG2;
+wire VCC4, VCC6, VCC9, VCC11;
+wire VBG;
+
+/* instantiate the Rita! */
+
+rita_rf_chip rita (.GND(GND),
+		   .CLK(Ctrl_CLK),
+		   .DATA(Ctrl_DATA),
+		   .STROBE(Ctrl_STROBE),
+		   .RESETZ(Ctrl_RESETZ),
+		   .IN(IN),
+		   .IP(IP),
+		   .QN(QN),
+		   .QP(QP),
+		   .LNAGSMN(LNAGSMN),
+		   .LNAGSMP(LNAGSMP),
+		   .LNADCSN(LNADCSN),
+		   .LNADCSP(LNADCSP),
+		   .LNAPCSN(LNAPCSN),
+		   .LNAPCSP(LNAPCSP),
+		   .LBTXOUT(LBTXOUT),
+		   .HBTXOUT(HBTXOUT),
+		   .DAC(DAC),
+		   .DET1(DET1),
+		   .DET2(DET2),
+		   .APC(APC),
+		   .RTEMP_VTEST(RTEMP_VTEST),
+		   .SIOUT_TST(),	/* no connect */
+		   .TSTVCO1(),		/* ditto */
+		   .TSTVCO2(),		/* "" */
+		   .VBAT1(VBAT),
+		   .VBAT2(VBAT),
+		   .VREG1(VREG1),
+		   .VREG2(VREG2),
+		   .VREG3(VREG3),
+		   .VRIO(VRIO),
+		   .VCC1(VREG2),
+		   .VCC2(VREG2),
+		   .VCC3(VREG2),
+		   .VCC4(VCC4),
+		   .VCC5(VREG2),
+		   .VCC6(VCC6),
+		   .VCC7(VREG1),
+		   .VCC8(VREG3),
+		   .VCC9(VCC9),
+		   .VCC10(VREG3),
+		   .VCC11(VCC11),
+		   .VCC12(VREG1),
+		   .VCC13(VREG1),
+		   .VBG(VBG),
+		   .XEN(XEN),
+		   .XSEL(XSEL),
+		   .XIN(XIN),
+		   .XOUT(Clock_out_to_DBB)
+		);
+
+/* bypass caps on VREGn */
+capacitor C619 (VREG1, GND);
+capacitor C622 (VREG2, GND);
+capacitor C613 (VREG3, GND);
+
+/* caps on VCCn */
+
+/* VCC1  */ capacitor C629 (VREG2, GND);
+/* VCC2  */ capacitor C630 (VREG2, GND);
+/* VCC3  */ capacitor C631 (VREG2, GND);
+/* VCC4  */ capacitor C632 (VCC4,  GND);
+/* VCC5  */ capacitor C633 (VREG2, GND);
+/* VCC6  */ capacitor C634 (VCC6,  GND);
+/* VCC7  */ capacitor C620 (VREG1, GND);
+/* VCC8  */ capacitor C609 (VREG3, GND);
+/* VCC9  */ capacitor C608 (VCC9,  GND);
+/* VCC10 */ capacitor C607 (VREG3, GND);
+/* VCC11 */ capacitor C606 (VCC11, GND);
+/* VCC12 */ capacitor C610 (VREG1, GND);
+/* VCC13 */ capacitor C617 (VREG1, GND);
+
+capacitor C616 (VBG, GND);
+
+capacitor XEN_cap (XEN, GND);
+capacitor XEN_cap2 (XEN, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/xtal_32khz_wrap.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,13 @@
+/*
+ * The 32 kHz crystal resonator package used in the TR-800 module
+ * only has the two electrodes as pads, no ground pad.
+ * We shall use the same type of crystal on FC Venus.
+ */
+
+module xtal_32khz_wrap (electrode1, electrode2, GND);
+
+input electrode1, electrode2, GND;
+
+xtal_2pin_pkg xtal (electrode1, electrode2);
+
+endmodule