| Wed, 01 Dec 2021 06:50:25 +0000 |
Mychaela Falconia |
buzzer component nailed down
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| Wed, 01 Dec 2021 04:08:35 +0000 |
Mychaela Falconia |
loudspeaker block implemented
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| Wed, 01 Dec 2021 03:26:15 +0000 |
Mychaela Falconia |
HSO audio channel implemented
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| Wed, 01 Dec 2021 02:22:39 +0000 |
Mychaela Falconia |
main audio channel implemented
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| Sat, 27 Nov 2021 20:43:23 +0000 |
Mychaela Falconia |
VSP sniff tap implemented
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| Sat, 27 Nov 2021 20:01:56 +0000 |
Mychaela Falconia |
add VBAT tap for calibration measurements
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| Sat, 27 Nov 2021 19:46:01 +0000 |
Mychaela Falconia |
LPG and PWL LEDs implemented
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| Sat, 27 Nov 2021 19:16:58 +0000 |
Mychaela Falconia |
MCL: prebiased transistor pair parts
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| Sat, 27 Nov 2021 18:34:05 +0000 |
Mychaela Falconia |
ON_nOFF indicator LED implemented
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| Sat, 27 Nov 2021 07:03:14 +0000 |
Mychaela Falconia |
keypad initial implementation
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| Sat, 27 Nov 2021 04:43:53 +0000 |
Mychaela Falconia |
Verilog src: preparations for adding the keypad
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| Sat, 27 Nov 2021 04:25:30 +0000 |
Mychaela Falconia |
MCL: preliminary part selection for keypad switches
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| Sat, 27 Nov 2021 02:46:19 +0000 |
Mychaela Falconia |
LCD subsystem integrated
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| Sat, 27 Nov 2021 02:09:46 +0000 |
Mychaela Falconia |
progress toward LCD integration
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| Sat, 27 Nov 2021 01:43:32 +0000 |
Mychaela Falconia |
MAX1916.v and lcd_module.v from lunalcd2
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| Sat, 27 Nov 2021 01:34:05 +0000 |
Mychaela Falconia |
74LVC2G125 buffer for BL control captured at MCL level
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| Sat, 27 Nov 2021 01:09:05 +0000 |
Mychaela Falconia |
MCL and primitives: LCD and MAX1916 from lunalcd2
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| Sat, 27 Nov 2021 00:25:20 +0000 |
Mychaela Falconia |
add top README
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| Fri, 26 Nov 2021 23:45:48 +0000 |
Mychaela Falconia |
add missing bypass caps for mobile domain peripherals
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| Fri, 26 Nov 2021 23:32:00 +0000 |
Mychaela Falconia |
charging_circuit structural module contains no connections to GND
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| Fri, 26 Nov 2021 23:18:12 +0000 |
Mychaela Falconia |
use buffer_slot_od primitive for slots of 74LVC2G07
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| Fri, 26 Nov 2021 23:08:09 +0000 |
Mychaela Falconia |
implement USB domain load resistor as proposed in document
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| Fri, 26 Nov 2021 23:02:19 +0000 |
Mychaela Falconia |
venus/doc/USB-and-mobile-domains treatise written
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| Wed, 24 Nov 2021 18:14:11 +0000 |
Mychaela Falconia |
venus/doc/MEMIF-fixed-2.8V: explanatory article
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| Mon, 22 Nov 2021 19:19:59 +0000 |
Mychaela Falconia |
eliminate R209 and tie Iota VLMEM directly to UPR
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| Mon, 22 Nov 2021 09:54:48 +0000 |
Mychaela Falconia |
starpoints in core: commit to using pcb-rnd intnoconn
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| Mon, 22 Nov 2021 03:25:55 +0000 |
Mychaela Falconia |
charging LED circuit captured
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| Mon, 22 Nov 2021 03:03:15 +0000 |
Mychaela Falconia |
intnoconn approach to charging current sense resistor
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| Sun, 21 Nov 2021 20:20:38 +0000 |
Mychaela Falconia |
Venus src: charging circuit captured
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| Sun, 21 Nov 2021 08:58:43 +0000 |
Mychaela Falconia |
Venus MCL: use new ipc-diode.pinout, add SS34 for charging
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| Sun, 21 Nov 2021 08:40:13 +0000 |
Mychaela Falconia |
Venus MCL: add Q401 charging circuit MOSFET
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| Sun, 21 Nov 2021 03:14:56 +0000 |
Mychaela Falconia |
venus/src/Makefile: generate bound.unet
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| Sun, 21 Nov 2021 03:05:26 +0000 |
Mychaela Falconia |
Venus MCL: ready for first binding
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| Sun, 21 Nov 2021 02:14:49 +0000 |
Mychaela Falconia |
Venus MCL: first steps toward binding,
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| Sat, 20 Nov 2021 21:54:27 +0000 |
Mychaela Falconia |
Venus: reached the point of compiling sverp.unet
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| Sat, 20 Nov 2021 21:12:23 +0000 |
Mychaela Falconia |
Venus: preliminary choice of slide switch part for charging control
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| Sat, 20 Nov 2021 19:44:59 +0000 |
Mychaela Falconia |
Venus src: USB domain captured
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| Sat, 20 Nov 2021 17:48:18 +0000 |
Mychaela Falconia |
venus/src/usb: building blocks from DUART28
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| Sat, 20 Nov 2021 09:10:02 +0000 |
Mychaela Falconia |
Venus primitives: additions for USB
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| Sat, 20 Nov 2021 08:32:54 +0000 |
Mychaela Falconia |
Venus MCL: smaller package for USB EEPROM
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| Sat, 20 Nov 2021 06:19:00 +0000 |
Mychaela Falconia |
Venus MCL: USB connector and ICs from DUART28
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| Sat, 20 Nov 2021 05:45:37 +0000 |
Mychaela Falconia |
venus/src/top/mobile.v written
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| Sat, 20 Nov 2021 04:32:50 +0000 |
Mychaela Falconia |
Venus src: jtag_if.v adapted from FCDEV3B
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| Fri, 19 Nov 2021 20:59:14 +0000 |
Mychaela Falconia |
Venus src: SIM socket block captured
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| Fri, 19 Nov 2021 20:35:10 +0000 |
Mychaela Falconia |
Venus src: add 74LVC1G04 inverting buffer for SIM_CD
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| Fri, 19 Nov 2021 20:10:46 +0000 |
Mychaela Falconia |
venus/src/periph/calypso_uart_in.v written
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| Fri, 19 Nov 2021 19:46:03 +0000 |
Mychaela Falconia |
Venus primitives: add logic IC subpackages
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| Fri, 19 Nov 2021 18:57:57 +0000 |
Mychaela Falconia |
Venus MCL: add 74LVC125A for Calypso UART inputs
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| Fri, 19 Nov 2021 06:48:25 +0000 |
Mychaela Falconia |
venus/src/periph/battery.v: adapted from FCDEV3B
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| Fri, 19 Nov 2021 06:44:53 +0000 |
Mychaela Falconia |
venus/src/periph/sma_wrap.v: unchanged from FCDEV3B
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| Fri, 19 Nov 2021 06:09:13 +0000 |
Mychaela Falconia |
Venus core: bring out SIM_CD
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| Fri, 19 Nov 2021 05:58:21 +0000 |
Mychaela Falconia |
Venus: first version of Verilog for the Calypso core
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| Fri, 19 Nov 2021 03:47:49 +0000 |
Mychaela Falconia |
Venus primitives: add TRRS jack
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| Fri, 19 Nov 2021 03:44:51 +0000 |
Mychaela Falconia |
Venus MCL: add audio jacks
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| Fri, 19 Nov 2021 03:07:48 +0000 |
Mychaela Falconia |
Venus primitives file started
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| Fri, 19 Nov 2021 01:43:41 +0000 |
Mychaela Falconia |
Venus MCL: add LEDs
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