FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/L1/cust0/l1_rf8.h @ 858:4c6e7ada647b

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compressed trace decoder almost fully implemented
author Space Falcon <falcon@ivan.Harhan.ORG>
date Sat, 02 May 2015 08:08:26 +0000
parents 26472940e5b0
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename l1_rf8.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 #ifndef __L1_RF_H__
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10 #define __L1_RF_H__
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11
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12 /************************************/
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13 /* SYNTHESIZER setup time... */
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14 /************************************/
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15
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16 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) //RX Synthesizer setup time in qbit.
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17 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
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18
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19
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20 /************************************/
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21 /* time for TPU scenario ending... */
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22 /************************************/
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23
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24 #define RX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BDLENA down
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25 // minus serialization time
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26 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BULON down
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27 // minus serialization time
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28
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29 /******************************************************/
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30 /* TXPWR configuration... */
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31 /* Fixed TXPWR value when GSM management is disabled. */
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32 /******************************************************/
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33
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34 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
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35 // #define FIXED_TXPWR ((0xFC << 6) | AUXAPC | FALSE) // TXPWR=10, value=252
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36 // #define FIXED_TXPWR ((0x28 << 6) | AUXAPC | FALSE)
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37 #define FIXED_TXPWR ((0x68 << 6) | AUXAPC | FALSE) // TXPWR=15
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38 #endif
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39
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40
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41 /************************************/
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42 /*(ANALOG)delay (in qbits) */
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43 /************************************/
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44
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45 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
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46 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
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47 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
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48
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49 #if (ANALOG == 1)
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50 #define UL_ABB_DELAY 0 // modulator input to output delay, theoretical value is 6, needs to be checked
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51 #endif
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52
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53 #if ((ANALOG == 2) || (ANALOG == 3))
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54 #define UL_ABB_DELAY 3 // modulator input to output delay
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55 #endif
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56
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57 /************************************/
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58 /* TX Propagation delay... */
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59 /************************************/
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60
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61 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
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62 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
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63 #endif
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64
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65 /************************************/
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66 /* Initial value for APC DELAY */
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67 /************************************/
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68
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69 #if (ANALOG == 1)
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70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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71 #define APCDEL_DOWN 2 // minimum value: 2
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72 #define APCDEL_UP (6+5) // minimum value: 6
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73 #endif
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74
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75 #if (ANALOG == 2) || (ANALOG == 3)
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76 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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77 #define APCDEL_DOWN (2+0) // minimum value: 2
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78 #define APCDEL_UP (6+2) // minimum value: 6
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79 #endif
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80
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81 #define GUARD_BITS 7
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82
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83 /************************************/
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84 /* Initial value for AFC... */
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85 /************************************/
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86
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87 #define EEPROM_AFC ((-1180)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
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88
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89 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF BAND GAP(in Frames)
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90 // !! minimum Value : 1 Frame due to the fact there is no
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91 // hisr() in the first wake-up frame !!!!
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92
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93 /************************************/
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94 /* Baseband registers */
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95 /************************************/
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96
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97 #if (ANALOG == 1)
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98 // Omega registers values will be programmed at 1st DSP communication interrupt
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99 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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100 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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101 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
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102 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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103 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
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104 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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105 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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106 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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107 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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108 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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109
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110 // BULRUDEL will be initialized on rach only ....
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111 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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112 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
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113 #endif
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114
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115 #if (ANALOG == 2)
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116 // IOTA registers values will be programmed at 1st DSP communication interrupt
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117 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
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118 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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119 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
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120 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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121 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
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122 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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123 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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124 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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125 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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126 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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127 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
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128
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129 // BULRUDEL will be initialized on rach only ....
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130 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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131 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) //
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132
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133 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
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134 // Monoslot, Vpp=8/15*Vref
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135 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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136 #endif
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137
152
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138 #if (ANALOG == 3)
151
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139 // SYREN registers values will be programmed at 1st DSP communication interrupt
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140 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
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141 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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142 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3dB
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143 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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144 #define C_APCOFF ((0x07C << 6) | APCOFF | TRUE)
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145 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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146 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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147 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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148 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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149 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
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150 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
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151
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152 // BULRUDEL will be initialized on rach only ....
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153 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
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154 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
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155 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
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156 // Monoslot, Vpp=8/15*Vref
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157 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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158
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159 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
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160 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
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161 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
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162 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
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163 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
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164 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
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165
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166 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
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167
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168 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
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169
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170 #endif
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171
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172
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173 /************************************/
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174 /* Automatic frequency compensation */
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175 /************************************/
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176 /********************* C_Psi_sta definition *****************************/
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177 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
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178 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
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179 /* regarding Vega V/N = 2.4/4096 */
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180 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
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181 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
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182 /* = 0.000195748 */
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183 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
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184 /************************************************************************/
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185
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186 #define C_Psi_sta_inv 11677L // (1/C_Psi_sta)
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187 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
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188 #define C_Psi_st_32 294257L // F0.32
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189 #define C_Psi_st_inv 14596L // (1/C_Psi_st)
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190
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191 typedef struct
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192 {
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193 WORD16 eeprom_afc;
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194 UWORD32 psi_sta_inv;
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195 UWORD32 psi_st;
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196 UWORD32 psi_st_32;
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197 UWORD32 psi_st_inv;
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198 }
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199 T_AFC_PARAMS;
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200
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201 /************************************/
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202 /* Swap IQ definitions... */
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203 /************************************/
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204 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
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205
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206 #define SWAP_IQ_GSM 0
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207 #define SWAP_IQ_DCS 3
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208 #define SWAP_IQ_PCS 3
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209 #define SWAP_IQ_GSM850 0 //TBD
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210
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211 /************************************/
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212 /* RF bands supported */
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213 /************************************/
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214
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215 #define RF_HW_BAND_SUPPORT (0x0020 | 0x0004) // radio_band_support E-GSM/DCS + PC
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216
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217 /************************************/
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218 /************************************/
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219 // typedef
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220 /************************************/
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221 /************************************/
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222
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223 /*************************************************************/
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224 /* Define structure for apc of TX Power ******/
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225 /*************************************************************/
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226
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227 typedef struct
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228 { // pcm-file "rf/tx/level.gsm|dcs"
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229 UWORD16 apc; // 0..31
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230 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
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231 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
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232 }
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233 T_TX_LEVEL;
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234
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235 /************************************/
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236 /* Automatic Gain Control */
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237 /************************************/
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238 /* Define structure for sub-band definition of TX Power ******/
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239
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240 typedef struct
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241 {
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242 UWORD16 upper_bound; //highest physical arfcn of the sub-band
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243 WORD16 agc_calib; // AGC for each TXPWR
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244 }T_RF_AGC_BAND;
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245
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246 /************************************/
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247 /* Ramp definitions */
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248 /************************************/
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249
152
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250 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
151
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251 typedef struct
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252 {
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253 UWORD8 ramp_up [16]; // Ramp-up profile
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254 UWORD8 ramp_down [16]; // Ramp-down profile
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255 }
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256 T_TX_RAMP;
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257 #endif
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258
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259
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260 // RF structure definition
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261 //========================
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262
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263 enum RfRevision {
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264 RF_IGNORE = 0x0000,
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265 RF_SL2 = 0x1000,
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266 RF_GAIA_20X = 0x2000,
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267 RF_GAIA_20A = 0x2001,
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268 RF_GAIA_20B = 0x2002,
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269 RF_ATLAS_20B = 0x2020,
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270 RF_PASCAL_20 = 0x2030
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271 };
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272
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273 // Number of bands supported
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274 #define GSM_BANDS 2
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275
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276 #define MULTI_BAND1 0
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277 #define MULTI_BAND2 1
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278
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279 // RF table sizes
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280 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
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281 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
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282
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283 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
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284 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
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285 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
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286 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
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287 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
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288
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289 #define AGC_TABLE_SIZE 36
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290
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291 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
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292
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293
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294 // RX parameters and tables
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295 //-------------------------
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296
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297 // AGC parameters and tables
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298 typedef struct
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299 {
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300 UWORD16 low_agc_noise_thr;
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301 UWORD16 high_agc_sat_thr;
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302 UWORD16 low_agc;
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303 UWORD16 high_agc;
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304 UWORD8 il2agc_pwr[121];
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305 UWORD8 il2agc_max[121];
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306 UWORD8 il2agc_av[121];
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307 }
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308 T_AGC;
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309
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310 // Calibration parameters
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311 typedef struct
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312 {
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313 UWORD16 g_magic;
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314 UWORD16 lna_att;
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315 UWORD16 lna_switch_thr_low;
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316 UWORD16 lna_switch_thr_high;
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317 }
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318 T_RX_CAL_PARAMS;
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319
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320 // RX temperature compensation
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321 typedef struct
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322 {
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323 WORD16 temperature;
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324 WORD16 agc_calib;
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325 }
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326 T_RX_TEMP_COMP;
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327
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328 // RF RX structure
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329 typedef struct
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330 {
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331 T_AGC agc;
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332 }
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333 T_RF_RX; //common
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334
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335 // RF RX structure
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336 typedef struct
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337 {
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338 T_RX_CAL_PARAMS rx_cal_params;
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339 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
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340 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
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341 }
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342 T_RF_RX_BAND;
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343
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344
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345 // TX parameters and tables
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346 //-------------------------
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347
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348 // TX temperature compensation
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349 typedef struct
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350 {
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351 WORD16 temperature;
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352 #if (ORDER2_TX_TEMP_CAL==1)
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353 WORD16 a;
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354 WORD16 b;
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355 WORD16 c;
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356 #else
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357 WORD16 apc_calib;
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358 #endif
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359 }
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360 T_TX_TEMP_CAL;
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361
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362
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363 // Ramp up and ramp down delay
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364 typedef struct
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365 {
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366 UWORD16 up;
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367 UWORD16 down;
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368 }
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369 T_RAMP_DELAY;
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370
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371 typedef struct
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372 {
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373 UWORD16 arfcn_limit;
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374 WORD16 chan_cal;
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375 }
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376 T_TX_CHAN_CAL;
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377
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378 // RF TX structure
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379 typedef struct
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380 {
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381 T_RAMP_DELAY ramp_delay;
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382 UWORD8 guard_bits; // number of guard bits needed for ramp up
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383 UWORD8 prg_tx;
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384 }
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385 T_RF_TX; //common
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386
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387 // RF TX structure
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388 typedef struct
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389 {
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390 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
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391 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
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392 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
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393 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
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394 }
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395 T_RF_TX_BAND;
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396
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397 // band structure
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398 typedef struct
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399 {
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400 T_RF_RX_BAND rx;
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diff changeset
401 T_RF_TX_BAND tx;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
402 UWORD8 swap_iq;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
403 }
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
404 T_RF_BAND;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
405
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
406 // RF structure
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
407 typedef struct
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
408 {
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parents:
diff changeset
409 // common for all bands
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
410 UWORD16 rf_revision;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
411 UWORD16 radio_band_support;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
412 T_RF_RX rx;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
413 T_RF_TX tx;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
414 T_AFC_PARAMS afc;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
415 }
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parents:
diff changeset
416 T_RF;
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parents:
diff changeset
417
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
418 /************************************/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
419 /* MADC definitions */
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parents:
diff changeset
420 /************************************/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
421 // Omega: 5 external channels if touch screen not used, 3 otherwise
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
422 enum ADC_INDEX {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
423 ADC_VBAT,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
424 ADC_VCHARG,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
425 ADC_ICHARG,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
426 ADC_VBACKUP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
427 ADC_BATTYP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
428 ADC_BATTEMP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
429 ADC_ADC3, // name of this ??
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
430 ADC_RFTEMP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
431 ADC_ADC4,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
432 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
433 };
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parents:
diff changeset
434
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
435 typedef struct
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
436 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
437 WORD16 converted[ADC_INDEX_END]; // converted
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
438 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
439 }
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
440 T_ADC;
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parents:
diff changeset
441
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
442 /************************************/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
443 /* MADC calibration */
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parents:
diff changeset
444 /************************************/
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parents:
diff changeset
445 typedef struct
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
446 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
447 UWORD16 a[ADC_INDEX_END];
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parents:
diff changeset
448 WORD16 b[ADC_INDEX_END];
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parents:
diff changeset
449 }
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parents:
diff changeset
450 T_ADCCAL;
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parents:
diff changeset
451
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
452 // Conversion table: ADC value -> temperature
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
453 typedef struct
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parents:
diff changeset
454 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
455 UWORD16 adc; // ADC reading is 10 bits
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
456 WORD16 temp; // temp is in approx. range -30..+80
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
457 }
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parents:
diff changeset
458 T_TEMP;
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parents:
diff changeset
459
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parents:
diff changeset
460 typedef struct
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parents:
diff changeset
461 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
462 char *name;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
463 void *addr;
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parents:
diff changeset
464 int size;
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parents:
diff changeset
465 }
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parents:
diff changeset
466 T_CONFIG_FILE;
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parents:
diff changeset
467
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parents:
diff changeset
468 typedef struct
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parents:
diff changeset
469 {
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parents:
diff changeset
470 char *name; // name of ffs file suffix
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parents:
diff changeset
471 T_RF_BAND *addr; // address to default flash structure
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
472 UWORD16 max_carrier; // max carrier
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
473 UWORD16 max_txpwr; // max tx power
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
474 }
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parents:
diff changeset
475 T_BAND_CONFIG;
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parents:
diff changeset
476
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
477 typedef struct
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parents:
diff changeset
478 {
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parents:
diff changeset
479 UWORD8 band[GSM_BANDS]; // index to band address
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
480 UWORD8 txpwr_tp; // tx power turning point
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
481 UWORD16 first_arfcn; // first index
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
482 }
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parents:
diff changeset
483 T_STD_CONFIG;
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parents:
diff changeset
484
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
485 enum GSMBAND_DEF
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
486 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
487 BAND_NONE,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
488 BAND_EGSM900,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
489 BAND_DCS1800,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
490 BAND_PCS1900,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
491 BAND_GSM850,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
492 // put new bands here
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
493 BAND_GSM900 //last entry
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parents:
diff changeset
494 };
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parents:
diff changeset
495
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parents:
diff changeset
496
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parents:
diff changeset
497 /************************************/
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parents:
diff changeset
498 /* ABB (Omega) Initialization */
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parents:
diff changeset
499 /************************************/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
500
152
26472940e5b0 l1_rf<N>.h headers preened
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parents: 151
diff changeset
501 #if ((ANALOG == 1) || (ANALOG == 2))
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
502 #define ABB_TABLE_SIZE 16
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
503 #endif
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parents:
diff changeset
504
152
26472940e5b0 l1_rf<N>.h headers preened
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parents: 151
diff changeset
505 #if (ANALOG == 3)
151
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parents:
diff changeset
506 #define ABB_TABLE_SIZE 22
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parents:
diff changeset
507 #endif
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parents:
diff changeset
508
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
509 // Note that this translation is probably not needed at all. But until L1 is
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
510 // (maybe) changed to simply initialize the ABB from a table of words, we
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
511 // use this to make things more easy-readable.
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
512
152
26472940e5b0 l1_rf<N>.h headers preened
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parents: 151
diff changeset
513 #if (ANALOG == 1)
151
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parents:
diff changeset
514 enum ABB_REGISTERS {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
515 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
516 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
517 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
518 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
519 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
520 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
521 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
522 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
523 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
524 ABB_VBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
525 ABB_APCDEL1
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
526 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
527 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
528
152
26472940e5b0 l1_rf<N>.h headers preened
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 151
diff changeset
529 #if (ANALOG == 2)
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
530 enum ABB_REGISTERS {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
531 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
532 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
533 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
534 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
535 ABB_BULGCAL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
536 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
537 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
538 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
539 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
540 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
541 ABB_VBCTRL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
542 ABB_VBCTRL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
543 ABB_APCDEL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
544 ABB_APCDEL2
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
545 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
546 #endif
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parents:
diff changeset
547
152
26472940e5b0 l1_rf<N>.h headers preened
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548 #if (ANALOG == 3)
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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549 enum ABB_REGISTERS {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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550 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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551 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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552 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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553 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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554 ABB_BULGCAL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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555 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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556 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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557 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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558 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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559 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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560 ABB_VBCTRL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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561 ABB_VBCTRL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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562 ABB_APCDEL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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563 ABB_APCDEL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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564 ABB_VBPOP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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565 ABB_VAUDINITD,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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566 ABB_VAUDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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567 ABB_VAUOCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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568 ABB_VAUSCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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569 ABB_VAUDPLL
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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570 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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571 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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572 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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573