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comparison gsm-fw/L1/include/l1_confg.h @ 530:25a7fe25864c

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gsm-fw/L1/include: switch to LoCosto versions of all header files
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 01 Aug 2014 16:38:35 +0000
parents 80ee7eacdaeb
children de635895e0be
comparison
equal deleted inserted replaced
529:f72c9db5e2f5 530:25a7fe25864c
1 /************* Revision Controle System Header ************* 1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software 2 * GSM Layer 1 software
3 * L1_CONFG.H 3 * L1_CONFG.H
4 * 4 *
5 * Filename l1_confg.h 5 * Filename l1_confg.h
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9 9
10 #ifndef __L1_CONFG_H__ 10 #ifndef __L1_CONFG_H__
11 #define __L1_CONFG_H__ 11 #define __L1_CONFG_H__
12
13 #ifndef _WINDOWS
14 #include "l1sw.cfg" // Configuration Software
15 #include "board.cfg"
16 #include "chipset.cfg"
17 #include "rf.cfg"
18 #include "swconfig.cfg"
19 #include "sys.cfg"
20 #endif
12 21
13 // Traces... 22 // Traces...
14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART 23 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack 24 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
16 // TRACE_TYPE == 1 -> L1/L3 interface trace 25 // TRACE_TYPE == 1 -> L1/L3 interface trace
30 // Code Version possible choices 39 // Code Version possible choices
31 //------------------------------ 40 //------------------------------
32 #define SIMULATION 1 41 #define SIMULATION 1
33 #define NOT_SIMULATION 2 42 #define NOT_SIMULATION 2
34 43
35 // RCL functions Version possible choices 44 // RLC functions Version possible choices
36 //------------------------------ 45 //------------------------------
37 #define POLL_FORCED 0 46 #define POLL_FORCED 0
38 #define RLC_SCENARIO 1 47 #define RLC_SCENARIO 1
39 #define MODEM_FLOW 2 48 #define MODEM_FLOW 2
40 49
41 // possible choices for UART trace output 50 // possible choices for UART trace output
42 //------------------------------ 51 //------------------------------
43 #define MODEM_UART 0 52 #if (CHIPSET != 15)
44 #define IRDA_UART 1 53 #define MODEM_UART 0
45 #if (CHIPSET == 12) 54 #define IRDA_UART 1
46 #define MODEM2_UART 2 55 #if (CHIPSET == 12)
56 #define MODEM2_UART 2
57 #endif
58 #else
59 // There is only one UART in Locosto
60 #define MODEM_UART 0
47 #endif 61 #endif
48 62
49 //============ 63 //============
50 // CODE CHOICE 64 // CODE CHOICE
51 //============ 65 //============
52 #if 0
53 #if (OP_L1_STANDALONE==0) 66 #if (OP_L1_STANDALONE==0)
54 #define CODE_VERSION NOT_SIMULATION 67 #define CODE_VERSION NOT_SIMULATION
55 #else // OP_L1_STANDALONE 68 #else // OP_L1_STANDALONE
56 #ifdef WIN32 69 #ifdef WIN32
57 #define CODE_VERSION SIMULATION 70 #define CODE_VERSION SIMULATION
58 #else // WIN32 71 #else // WIN32
59 #define CODE_VERSION NOT_SIMULATION 72 #define CODE_VERSION NOT_SIMULATION
60 #endif // WIN32 73 #endif // WIN32
61 #endif // OP_L1_STANDALONE 74 #endif // OP_L1_STANDALONE
62 #endif // #if 0
63
64 /* FreeCalypso */
65 #define CODE_VERSION NOT_SIMULATION
66 #define AMR 1
67 #define L1_12NEIGH 1
68 #define L1_DYN_DSP_DWNLD 0 /* for now */
69 #define L1_EOTD 0
70 #define L1_GTT 0
71 #define ORDER2_TX_TEMP_CAL 1
72 #define TRACE_TYPE 4
73 #define VCXO_ALGO 1
74
75 /* TESTMODE will be enabled with feature l1tm */
76
77 #if CONFIG_AUDIO
78 # define AUDIO_TASK 1 // Enable the L1 audio features
79 # define MELODY_E2 1
80 #endif
81
82 #if CONFIG_GPRS
83 # define L1_GPRS 1
84 #else
85 # define L1_GPRS 0
86 #endif
87
88 //--------------------------------------------------------------------------------- 75 //---------------------------------------------------------------------------------
89 // Test with full simulation. 76 // Test with full simulation.
90 //--------------------------------------------------------------------------------- 77 //---------------------------------------------------------------------------------
91 #if (CODE_VERSION == SIMULATION) 78 #if (CODE_VERSION == SIMULATION)
92 79
80
81 #undef FF_L1_IT_DSP_USF
82 #define FF_L1_IT_DSP_USF 0
83 #undef FF_L1_IT_DSP_DTX
84 #if (AMR == 1)
85 #define FF_L1_IT_DSP_DTX 1 //it should be 1, sajal- temp made it 0 for build purpose
86 #else
87 #define FF_L1_IT_DSP_DTX 0
88 #endif
89
90 #define L1_DRP_IQ_SCALING 0
91
93 // Test Scenari... 92 // Test Scenari...
94 #define SCENARIO_FILE 1 // Test Scenario comes from input files. 93 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
95 #define SCENARIO_MEM 0 // Test Scenario comes from RAM. 94 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
95
96 // In Simulation AUDIO_DEBUG Should be 0
97 #define AUDIO_DEBUG 0
96 98
97 // Traces... 99 // Traces...
98 #undef TRACE_TYPE 100 #undef TRACE_TYPE
99 #define TRACE_TYPE 5 101 #define TRACE_TYPE 5
100 #define LOGFILE_TRACE 1 // trace in an output logfile 102 #define LOGFILE_TRACE 1 // trace in an output logfile
103
104 #define BURST_PARAM_LOG_ENABLE 0 // Burst Param Log Enable
105
101 #define FLOWCHART 0 // Message sequence/flow chart trace. 106 #define FLOWCHART 0 // Message sequence/flow chart trace.
102 #define NUCLEUS_TRACE 0 // Nucleus error trace 107 #define NUCLEUS_TRACE 0 // Nucleus error trace
103 #define EOTD_TRACE 1 // EOTD log trace 108 #define EOTD_TRACE 1 // EOTD log trace
104 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error 109 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
105 110
106 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible. 111 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
107 112
108 // Control algorithms... 113 // Control algorithms...
109 #define AFC_ALGO 1 // AFC algorithm. 114 #define AFC_ALGO 1 // AFC algorithm.
115 #if (L1_SAIC != 0)
116 #define TOA_ALGO 2 // TOA algorithm.
117 #else
110 #define TOA_ALGO 1 // TOA algorithm. 118 #define TOA_ALGO 1 // TOA algorithm.
119 #endif
111 #define AGC_ALGO 1 // AGC algorithm. 120 #define AGC_ALGO 1 // AGC algorithm.
112 #define TA_ALGO 0 // TA (Timing Advance) algorithm. 121 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
113 #undef VCXO_ALGO 122 #undef VCXO_ALGO
114 #define VCXO_ALGO 0 // VCXO algo 123 #define VCXO_ALGO 1 // VCXO algo
115 #undef DCO_ALGO 124 #undef DCO_ALGO
116 #define DCO_ALGO 0 // DCO algo (TIDE) 125 #define DCO_ALGO 0 // DCO algo (TIDE)
117 #undef ORDER2_TX_TEMP_CAL 126 #undef ORDER2_TX_TEMP_CAL
118 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection 127 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
119 128
126 #define AUDIO_TASK 1 // Enable the L1 audio features 135 #define AUDIO_TASK 1 // Enable the L1 audio features
127 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1) 136 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
128 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) 137 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
129 138
130 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) 139 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
131 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401 140 #define TTY_SYNC_MCU 0 // TTY WORKAROUND BUG03401
132 #define TTY_SYNC_MCU_2 1 // 141 #define TTY_SYNC_MCU_2 0 //
133 #define L1_GTT_FIFO_TEST_ATOMIC 0 // 142 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
134 #define NEW_WKA_PATCH 0 143 #define NEW_WKA_PATCH 0
135 #define OPTIMISED 1 144 #define OPTIMISED 0
136 145
137 #define L1_RECOVERY 0 // L1 recovery 146 #define L1_RECOVERY 0 // L1 recovery
138 147
139 #undef L1_GPRS 148 #undef L1_GPRS
140 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities 149 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
154 #undef OP_RIV_AUDIO 163 #undef OP_RIV_AUDIO
155 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio 164 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
156 165
157 #undef OP_WCP 166 #undef OP_WCP
158 #define OP_WCP 0 // No WCP integration 167 #define OP_WCP 0 // No WCP integration
168
169 #undef L1_DRP
170 #define L1_DRP 0 // L1 supporting DRP interface
171
172 #undef DRP_MEM_SIMULATION
173 #define DRP_MEM_SIMULATION 0
159 //--------------------------------------------------------------------------------- 174 //---------------------------------------------------------------------------------
160 // Test with H/W platform. 175 // Test with H/W platform.
161 //--------------------------------------------------------------------------------- 176 //---------------------------------------------------------------------------------
177
178 #if (GSM_IDLE_RAM == 1)
179 #define GSM_IDLE_RAM_DEBUG 0
180 #endif
181
182 #define AFC_BYPASS_MODE 0
183 #define PWMEAS_IF_MODE_FORCE 0
184 // WA for OMAPS00099442 must be disabled in PC simulation
185 #undef L1_FF_WA_OMAPS00099442
186 #define L1_FF_WA_OMAPS00099442 0
187
162 #elif (CODE_VERSION == NOT_SIMULATION) 188 #elif (CODE_VERSION == NOT_SIMULATION)
163 189
164 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1) 190 #define L1_DRP_IQ_SCALING 1
191 // In Target AUDIO_DEBUG could be turned ON to debug any AUDIO ON/OFF issues
192 #define AUDIO_DEBUG 0
193
194 #if (GSM_IDLE_RAM == 1)
195 #if ((CHIPSET == 12) || (CHIPSET == 10))
196 #define GSM_IDLE_RAM_DEBUG 1
197 #else
198 #define GSM_IDLE_RAM_DEBUG 0
199 #endif
200 #else
201 #define GSM_IDLE_RAM_DEBUG 0
202 #endif
203
204 #define L1_VPM 1
205 #if (OP_L1_STANDALONE == 1)
206 #if (CHIPSET == 15)
207 #if ((BOARD == 71) && (FLASH == 0))
208 // Not possible in I-SAMPLE only RAM configuration as there will
209 // not be enough memory space
210 #define BURST_PARAM_LOG_ENABLE 0
211 #else
212 #define BURST_PARAM_LOG_ENABLE 1
213 #endif
214 #else
215 #define BURST_PARAM_LOG_ENABLE 0
216 #endif
217 #else
218 #define BURST_PARAM_LOG_ENABLE 0
219 #endif
220
165 // Work around about Calypso RevA: the bus is floating (Cf PB01435) 221 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
166 // (corrected with Calypso ReV B and Calypso C035) 222 // (corrected with Calypso ReV B and Calypso C035)
167 #if (CHIPSET == 7) 223 #if (CHIPSET == 7)
168 #define W_A_CALYPSO_BUG_01435 1 224 #define W_A_CALYPSO_BUG_01435 1
169 #else 225 #else
170 #define W_A_CALYPSO_BUG_01435 0 226 #define W_A_CALYPSO_BUG_01435 0
171 #endif 227 #endif
172 228
229 #if (CHIPSET == 12) // Not needed for CHIPSET =15, as there is no extended page mode in Locosto
230 #define W_A_CALYPSO_PLUS_SPR_19599 1
231 #else
232 #define W_A_CALYPSO_PLUS_SPR_19599 0
233 #endif
173 234
174 // for AMR thresolds definition CQ22226 235 // for AMR thresolds definition CQ22226
175 #define AMR_THRESHOLDS_WORKAROUND 1 236 #define W_A_AMR_THRESHOLDS 1
237 #define W_A_PCTM_RX_AGC_GLOBAL_PARAMS 1 // For support of PCTM
176 238
177 #if (L1_GTT==1) 239 #if (L1_GTT==1)
178 #define TTY_SYNC_MCU 1 240 #define TTY_SYNC_MCU 0
179 #define TTY_SYNC_MCU_2 1 241 #define TTY_SYNC_MCU_2 0
180 #define L1_GTT_FIFO_TEST_ATOMIC 0 242 #define L1_GTT_FIFO_TEST_ATOMIC 0
181 #define NEW_WKA_PATCH 0 243 #define NEW_WKA_PATCH 0
182 #define OPTIMISED 1 244 #define OPTIMISED 0
183 #else 245 #else
184 #define TTY_SYNC_MCU_2 0 246 #define TTY_SYNC_MCU_2 0
185 #define L1_GTT_FIFO_TEST_ATOMIC 0 247 #define L1_GTT_FIFO_TEST_ATOMIC 0
186 #define TTY_SYNC_MCU 0 248 #define TTY_SYNC_MCU 0
187 #define NEW_WKA_PATCH 0 249 #define NEW_WKA_PATCH 0
188 #define OPTIMISED 0 250 #define OPTIMISED 0
189 251
190 #endif 252 #endif
191 253
254 #undef FF_L1_IT_DSP_USF
255 #if (L1_GPRS == 1)
256 #define FF_L1_IT_DSP_USF 1
257 #else
258 #define FF_L1_IT_DSP_USF 0
259 #endif
260 #undef FF_L1_IT_DSP_DTX
261 #if (AMR == 1)
262 #define FF_L1_IT_DSP_DTX 1
263 #else
264 #define FF_L1_IT_DSP_DTX 0
265 #endif
266
192 // Traces... 267 // Traces...
193 #define NUCLEUS_TRACE 0 // Nucleus error trace 268 #define NUCLEUS_TRACE 0 // Nucleus error trace
194 #define FLOWCHART 0 // Message sequence/flow chart trace. 269 #define FLOWCHART 0 // Message sequence/flow chart trace.
195 #define LOGFILE_TRACE 0 // trace in an output logfile 270 #define LOGFILE_TRACE 0 // trace in an output logfile
196 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error 271 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
206 #endif 281 #endif
207 282
208 // Control algorithms... 283 // Control algorithms...
209 #define AFC_ALGO 1 // AFC algorithm. 284 #define AFC_ALGO 1 // AFC algorithm.
210 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!! 285 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
286 #if (L1_SAIC != 0)
287 #define TOA_ALGO 2 // TOA algorithm.
288 #else
211 #define TOA_ALGO 1 // TOA algorithm. 289 #define TOA_ALGO 1 // TOA algorithm.
290 #endif
212 #define AGC_ALGO 1 // AGC algorithm. 291 #define AGC_ALGO 1 // AGC algorithm.
213 #define TA_ALGO 1 // TA (Timing Advance) algorithm. 292 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
214 293
215 #define FACCH_TEST 0 // FACCH test enabled. 294 #define FACCH_TEST 0 // FACCH test enabled.
216 295
217 #define ADC_TIMER_ON 0 // Timer for ADC measurements 296 #define ADC_TIMER_ON 0 // Timer for ADC measurements
218 #define AFC_ON 1 // Enable of the Omega AFC module 297 #define AFC_ON 1 // Enable of the Omega AFC module
219 298
220 #if 0
221 /* FreeCalypso: moved to config section above */
222 #define AUDIO_TASK 1 // Enable the L1 audio features 299 #define AUDIO_TASK 1 // Enable the L1 audio features
223 #endif
224 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1) 300 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
225 #if (OP_L1_STANDALONE == 1) 301 #if (OP_L1_STANDALONE == 1)
226 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) 302 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
227 #else 303 #else
228 #define AUDIO_L1_STANDALONE 0 304 #define AUDIO_L1_STANDALONE 0
229 #endif 305 #endif
230 306
231 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) 307 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
232 308
233 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management 309 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
234 310
235 #define L1_RECOVERY 1 // L1 recovery 311 #define L1_RECOVERY 1 // L1 recovery
236 312
313 #if ((RF_FAM == 60) || (RF_FAM == 61))
314 #define L1_DRP 1 // L1 supporting DRP interface
315 #else
316 #define L1_DRP 0 // L1 supporting DRP interface
317 #endif
318 #define DRP_MEM_SIMULATION 0 // DRP memory simulation OFF by default
237 319
238 #if (L1_GPRS == 1) 320 #if (L1_GPRS == 1)
239 #define RLC_VERSION RLC_SCENARIO 321 #define RLC_VERSION RLC_SCENARIO
240 #if (RLC_VERSION == RLC_SCENARIO) 322 #if (RLC_VERSION == RLC_SCENARIO)
241 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO 323 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
257 339
258 #else 340 #else
259 #define DSP_BACKGROUND_TASKS 0 341 #define DSP_BACKGROUND_TASKS 0
260 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it 342 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
261 #endif 343 #endif
344 #define PWMEAS_IF_MODE_FORCE 1
345 // WA for OMAPS00099442 (OMAPS0010023 (N12.x), OMAPS000010022 (N5.x))
346 // The problem is: When NW is lost due to reception gap or cell border range,
347 // the MS will try to re-synchronize on the cell with the TPU timing aligned
348 // with the timing of the cell. So the FB will start within the 92 bits of the TPU window and
349 // will be missed. This issue is due to a limitation of the legacy FB demodulation algorithm
350 // WA is to re-initialize the TPU with an arbitrary timing value
351 #undef L1_FF_WA_OMAPS00099442
352 #define L1_FF_WA_OMAPS00099442 1
353
262 #endif 354 #endif
263 355
264 // Audio tasks selection 356 // Audio tasks selection
265 //----------------------- 357 //-----------------------
266 358
269 #define TONE 1 // Enable tone feature 361 #define TONE 1 // Enable tone feature
270 // Temporary modification for protocol stack compatibility - GSMLITE will be removed 362 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
271 #if (OP_L1_STANDALONE == 1) 363 #if (OP_L1_STANDALONE == 1)
272 #define GSMLITE 1 364 #define GSMLITE 1
273 #endif 365 #endif
366 #if (CODE_VERSION == SIMULATION)
367 #define L1_VOICE_MEMO 1
368 #endif
274 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE)) 369 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
275 #define MELODY_E1 1 // Enable melody format E1 feature 370 #define MELODY_E1 1 // Enable melody format E1 feature
276 #define VOICE_MEMO 1 // Enable voice memorization feature 371
277 372 #if(L1_VOICE_MEMO == 1)
373 #define VOICE_MEMO 1 // Enable voice memorization feature
374 #else
375 #define VOICE_MEMO 0
376 #endif
278 #define FIR 1 // Enable FIR feature 377 #define FIR 1 // Enable FIR feature
279 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) 378 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
280 #define AUDIO_MODE 1 // Enable Audio mode feature 379 #define AUDIO_MODE 1 // Enable Audio mode feature
281 #else 380 #else
282 #define AUDIO_MODE 0 // Disable Audio mode feature 381 #define AUDIO_MODE 0 // Disable Audio mode feature
283 #endif 382 #endif
284 #else 383 #else
285 #define MELODY_E1 0 // Disable melody format E1 feature 384 #define MELODY_E1 0 // Disable melody format E1 feature
286 #define VOICE_MEMO 0 // Disable voice memorization feature 385 #if(L1_VOICE_MEMO == 1)
386 #define VOICE_MEMO 1 // Enable voice memorization feature
387 #else
388 #define VOICE_MEMO 0
389 #endif
287 #if (MELODY_E2) 390 #if (MELODY_E2)
288 #define FIR 1 // Enable FIR feature 391 #define FIR 1 // Enable FIR feature
289 #else 392 #else
290 #define FIR 0 // Disable FIR feature 393 #define FIR 0 // Disable FIR feature
291 #endif 394 #endif
292
293 #define AUDIO_MODE 0 // Disable Audio mode feature 395 #define AUDIO_MODE 0 // Disable Audio mode feature
294 #endif 396 #endif
295 // Define CPORT for ESample only 397
296 #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36)))
297 #define L1_CPORT 1 // Enable cport feature
298 #else
299 #define L1_CPORT 0 // Disable cport feature
300 #endif
301 398
302 #else 399 #else
303 #define KEYBEEP 0 // Enable keybeep feature 400 #define KEYBEEP 0 // Enable keybeep feature
304 #define TONE 0 // Enable tone feature 401 #define TONE 0 // Enable tone feature
305 #define MELODY_E1 0 // Enable melody format E1 feature 402 #define MELODY_E1 0 // Enable melody format E1 feature
306 #define VOICE_MEMO 0 // Enable voice memorization feature 403 #define VOICE_MEMO 0 // Enable voice memorization feature
307
308 #define FIR 0 // Enable FIR feature 404 #define FIR 0 // Enable FIR feature
309 #define AUDIO_MODE 0 // Enable Audio mode feature 405 #define AUDIO_MODE 0 // Enable Audio mode feature
310 #define L1_CPORT 0 // Enable cport feature 406 #endif
311 #endif 407 #define L1_MIDI_BUFFER 1
312 408
313 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2 409 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
314 #if (OP_RIV_AUDIO == 1) 410 #if (OP_RIV_AUDIO == 1)
315 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available) 411 #define L1_AUDIO_DRIVER (L1_VOICE_MEMO_AMR | L1_EXT_AUDIO_MGT | L1_MP3) // Riviera audio driver (only Voice Memo AMR is available)
316 #endif 412 #endif
317 413
318 414
319 // Vocoder selections 415 // Vocoder selections
320 //------------------- 416 //-------------------
324 #define FR_EFR 3 // Full Rate + Enhanced Full Rate 420 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
325 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate 421 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
326 422
327 // Standard (frequency plan) selections 423 // Standard (frequency plan) selections
328 //------------------------------------- 424 //-------------------------------------
425 #if(L1_FF_MULTIBAND == 0) // std id is not used if multiband feature is enabled
329 426
330 #define GSM 1 // GSM900. 427 #define GSM 1 // GSM900.
331 #define GSM_E 2 // GSM900 Extended. 428 #define GSM_E 2 // GSM900 Extended.
332 #define PCS1900 3 // PCS1900. 429 #define PCS1900 3 // PCS1900.
333 #define DCS1800 4 // DCS1800. 430 #define DCS1800 4 // DCS1800.
334 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands) 431 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
335 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands) 432 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
336 #define GSM850 7 // GSM850 Band 433 #define GSM850 7 // GSM850 Band
337 #define DUAL_US 8 // PCS1900 + GSM850 434 #define DUAL_US 8 // PCS1900 + GSM850
338 435
436 #endif // L1_FF_MULTIBAND
437
339 /*------------------------------------*/ 438 /*------------------------------------*/
340 /* Power Management */ 439 /* Power Management */
341 /*------------------------------------*/ 440 /*------------------------------------*/
342 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1 441 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
343 442
344 443 /*------------------------------------*/
444 /* BT Audio */
445 /*------------------------------------*/
446 #if ((L1_MP3 == 1) || (L1_AAC == 1))
447 #if (OP_L1_STANDALONE == 0)
448 #if((PSP_STANDALONE == 1) || (DRP_FW_BUILD == 1))
449 #define L1_BT_AUDIO 0
450 #else
451 #define L1_BT_AUDIO 1
452 #endif
453 #else
454 #define L1_BT_AUDIO 0
455 #endif
456 #endif
345 /*---------------------------------------------------------------------------*/ 457 /*---------------------------------------------------------------------------*/
346 /* DSP configurations */ 458 /* DSP configurations */
347 /* ------------------ */ 459 /* ------------------ */
348 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */ 460 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */
349 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */ 461 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */
400 /*-------------------------------*/ 512 /*-------------------------------*/
401 #if (MELODY_E2) 513 #if (MELODY_E2)
402 // In case of the melody E2 the DSP trace must be disable because the 514 // In case of the melody E2 the DSP trace must be disable because the
403 // melody instrument waves are overlayed with DSP trace buffer 515 // melody instrument waves are overlayed with DSP trace buffer
404 516
405 // DSP debug trace API buufer config 517 // DSP debug trace API buffer config
406 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 518 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
407 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 519 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
408 #else 520 #else
409 // DSP debug trace API buufer config 521 // DSP debug trace API buffer config
410 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 522 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
411 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 523 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
412 #endif 524 #endif
413 525
414 #elif (DSP == 30) // First GPRS. 526 #elif (DSP == 30) // First GPRS.
467 #define CLKMOD2 0x4116 // ...65 Mips pll free 579 #define CLKMOD2 0x4116 // ...65 Mips pll free
468 #define CLKSTART 0x29 // ...65 Mips 580 #define CLKSTART 0x29 // ...65 Mips
469 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 581 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
470 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 582 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
471 #define AEC 1 // AEC/NS not supported. 583 #define AEC 1 // AEC/NS not supported.
472 #if (OP_RIV_AUDIO == 0) 584 #define L1_NEW_AEC 1
473 #define L1_NEW_AEC 1 585
474 #else
475 // Available but not yet tuned with Riviera AUDIO
476 #define L1_NEW_AEC 0
477 #endif
478 #if ((L1_NEW_AEC) && (!AEC)) 586 #if ((L1_NEW_AEC) && (!AEC))
479 // First undef the flag to avoid warnings at compilation time 587 // First undef the flag to avoid warnings at compilation time
480 #undef AEC 588 #undef AEC
481 #define AEC 1 589 #define AEC 1
482 #endif 590 #endif
490 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 598 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
491 #define ULYSSE 0 599 #define ULYSSE 0
492 600
493 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 601 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
494 602
495 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) 603 #if (CODE_VERSION == NOT_SIMULATION)
496
497 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 604 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
498
499 // management. 605 // management.
500 606 // DSP_IDLE3 is not supported in simulation
501 // DSP_IDLE3 is not supported in simulation
502
503 #else 607 #else
504 #define W_A_DSP_IDLE3 0 608 #define W_A_DSP_IDLE3 0
505 #endif 609 #endif
506 610
507 // DSP software work-around config 611 // DSP software work-around config
508 // bit0 - Work-around to support CRTG. 612 // bit0 - Work-around to support CRTG.
509 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 613 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
510 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 614 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
511 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 615 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
512 616
513 #if (ANALOG == 1) // OMEGA / NAUSICA 617 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
514 #define C_DSP_SW_WORK_AROUND 0x0006 618 #define C_DSP_SW_WORK_AROUND 0x0006
515 619
516 #elif (ANALOG == 2) // IOTA 620 #elif (ANLG_FAM == 2) // IOTA
517 #define C_DSP_SW_WORK_AROUND 0x000E 621 #define C_DSP_SW_WORK_AROUND 0x000E
518 622
519 #elif (ANALOG == 3) // SYREN 623 #elif (ANLG_FAM == 3) // SYREN
520 #define C_DSP_SW_WORK_AROUND 0x000E 624 #define C_DSP_SW_WORK_AROUND 0x000E
521 625
522 #endif 626 #endif
523 627
524 /* DSP debug trace configuration */ 628 /* DSP debug trace configuration */
525 /*-------------------------------*/ 629 /*-------------------------------*/
526 #if (MELODY_E2) 630 #if (MELODY_E2)
527 // In case of the melody E2 the DSP trace must be disable because the 631 // In case of the melody E2 the DSP trace must be disable because the
528 // melody instrument waves are overlayed with DSP trace buffer 632 // melody instrument waves are overlayed with DSP trace buffer
529 633
530 // DSP debug trace API buufer config 634 // DSP debug trace API buffer config
531 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 635 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
532 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 636 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
533 637
534 // DSP debug trace type config 638 // DSP debug trace type config
535 // |<-------------- Features -------------->|<---------- Levels ----------->| 639 // |<-------------- Features -------------->|<---------- Levels ----------->|
539 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 643 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
540 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 644 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
541 // Currently not supported ! 645 // Currently not supported !
542 #endif 646 #endif
543 #else 647 #else
544 // DSP debug trace API buufer config 648 // DSP debug trace API buffer config
545 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 649 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
546 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 650 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
547 651
548 // DSP debug trace type config 652 // DSP debug trace type config
549 // |<-------------- Features -------------->|<---------- Levels ----------->| 653 // |<-------------- Features -------------->|<---------- Levels ----------->|
550 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 654 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
551 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. 655 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
552 656
553 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 657 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
554 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 658 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
555 #endif 659 #endif
556 #endif 660 #endif
557 /* d_error_status */ 661 /* d_error_status */
558 /*-------------------------------*/ 662 /*-------------------------------*/
559 663
560 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 664 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
561 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 665 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
562 666
563 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 667 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
564 #define DSP_DEBUG_GSM_MASK 0x0000 668 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
565 #define DSP_DEBUG_GPRS_MASK 0x0f3d 669 #define DSP_DEBUG_GPRS_MASK 0x0f3d
566 #endif 670 #endif
567 671
568 #if DCO_ALGO 672 #if DCO_ALGO
569 // DCO type of scheduling 673 // DCO type of scheduling
575 #define CLKMOD2 0x4116 // ...65 Mips pll free 679 #define CLKMOD2 0x4116 // ...65 Mips pll free
576 #define CLKSTART 0x29 // ...65 Mips 680 #define CLKSTART 0x29 // ...65 Mips
577 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 681 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
578 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 682 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
579 #define AEC 1 // AEC/NS not supported. 683 #define AEC 1 // AEC/NS not supported.
580 #if (OP_RIV_AUDIO == 0) 684 #define L1_NEW_AEC 1
581 #define L1_NEW_AEC 1 685
582 #else
583 // Available but not yet tuned with Riviera AUDIO
584 #define L1_NEW_AEC 0
585 #endif
586 #if ((L1_NEW_AEC) && (!AEC)) 686 #if ((L1_NEW_AEC) && (!AEC))
587 // First undef the flag to avoid warnings at compilation time 687 // First undef the flag to avoid warnings at compilation time
588 #undef AEC 688 #undef AEC
589 #define AEC 1 689 #define AEC 1
590 #endif 690 #endif
597 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 697 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
598 #define ULYSSE 0 698 #define ULYSSE 0
599 699
600 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 700 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
601 701
602 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) 702 #if (CODE_VERSION == NOT_SIMULATION)
603 703 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
604 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 704 // management.
605 705 // DSP_IDLE3 is not supported in simulation
606 // management.
607
608 // DSP_IDLE3 is not supported in simulation
609
610 #else 706 #else
611 #define W_A_DSP_IDLE3 0 707 #define W_A_DSP_IDLE3 0
612 #endif 708 #endif
613 709
614 // DSP software work-around config 710 // DSP software work-around config
615 // bit0 - Work-around to support CRTG. 711 // bit0 - Work-around to support CRTG.
616 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 712 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
617 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 713 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
618 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 714 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
619 #if (ANALOG == 1) // OMEGA / NAUSICA 715 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
620 #define C_DSP_SW_WORK_AROUND 0x0006 716 #define C_DSP_SW_WORK_AROUND 0x0006
621 717
622 #elif (ANALOG == 2) // IOTA 718 #elif (ANLG_FAM == 2) // IOTA
623 #define C_DSP_SW_WORK_AROUND 0x000E 719 #define C_DSP_SW_WORK_AROUND 0x000E
624 720
625 #elif (ANALOG == 3) // SYREN 721 #elif (ANLG_FAM == 3) // SYREN
626 #define C_DSP_SW_WORK_AROUND 0x000E 722 #define C_DSP_SW_WORK_AROUND 0x000E
627 723
628 #endif 724 #endif
629 725
630 /* DSP debug trace configuration */ 726 /* DSP debug trace configuration */
631 /*-------------------------------*/ 727 /*-------------------------------*/
632 #if (MELODY_E2) 728 #if (MELODY_E2)
633 // In case of the melody E2 the DSP trace must be disable because the 729 // In case of the melody E2 the DSP trace must be disable because the
634 // melody instrument waves are overlayed with DSP trace buffer 730 // melody instrument waves are overlayed with DSP trace buffer
635 731
636 // DSP debug trace API buufer config 732 // DSP debug trace API buffer config
637 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 733 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
638 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 734 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
639 735
640 // DSP debug trace type config 736 // DSP debug trace type config
641 // |<-------------- Features -------------->|<---------- Levels ----------->| 737 // |<-------------- Features -------------->|<---------- Levels ----------->|
645 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 741 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
646 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 742 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
647 // Currently not supported ! 743 // Currently not supported !
648 #endif 744 #endif
649 #else 745 #else
650 // DSP debug trace API buufer config 746 // DSP debug trace API buffer config
651 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 747 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
652 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 748 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
653 749
654 // DSP debug trace type config 750 // DSP debug trace type config
655 // |<-------------- Features -------------->|<---------- Levels ----------->| 751 // |<-------------- Features -------------->|<---------- Levels ----------->|
656 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 752 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
657 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. 753 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
658 754
659 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 755 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
660 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 756 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
661 #endif 757 #endif
662 758
663 // AMR trace 759 // AMR trace
664 #define C_AMR_TRACE_ID 55 760 #define C_AMR_TRACE_ID 55
665 761
668 /*-------------------------------*/ 764 /*-------------------------------*/
669 765
670 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 766 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
671 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 767 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
672 768
673 // masks to apply on d_error_status bit field 769 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
674 #define DSP_DEBUG_GSM_MASK 0x0000 770 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
675 #define DSP_DEBUG_GPRS_MASK 0x0f3d 771 #define DSP_DEBUG_GPRS_MASK 0x0f3d
676 #endif 772 #endif
677 773
678 #elif (DSP == 35) // ROM Code GPRS AMR. 774 #elif (DSP == 35) // ROM Code GPRS AMR.
679 #define CLKMOD1 0x4006 // ... 775 #define CLKMOD1 0x4006 // ...
680 #define CLKMOD2 0x4116 // ...65 Mips pll free 776 #define CLKMOD2 0x4116 // ...65 Mips pll free
681 #define CLKSTART 0x29 // ...65 Mips 777 #define CLKSTART 0x29 // ...65 Mips
682 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 778 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
683 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 779 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
684 #define AEC 1 // AEC/NS not supported. 780 #define AEC 1 // AEC/NS not supported.
685 #if (OP_RIV_AUDIO == 0) 781 #define L1_NEW_AEC 1
686 #define L1_NEW_AEC 1 782
687 #else
688 // Available but not yet tuned with Riviera AUDIO
689 #define L1_NEW_AEC 0
690 #endif
691 #if ((L1_NEW_AEC) && (!AEC)) 783 #if ((L1_NEW_AEC) && (!AEC))
692 // First undef the flag to avoid warnings at compilation time 784 // First undef the flag to avoid warnings at compilation time
693 #undef AEC 785 #undef AEC
694 #define AEC 1 786 #define AEC 1
695 #endif 787 #endif
696 #define MAP 3 788 #define MAP 3
697 789
698 #define FF_L1_TCH_VOCODER_CONTROL 1 790 #define FF_L1_TCH_VOCODER_CONTROL 1
699 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 791 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
700 792
701 #define DSP_START 0x7000 793 #define DSP_START 0x7000
702 794
703 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer 795 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
704 796
705 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 797 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
706 #define ULYSSE 0 798 #define ULYSSE 0
707 799
708 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 800 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
709 801
710 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) 802 #if (CODE_VERSION == NOT_SIMULATION)
711 803 #if (CHIPSET != 12)
712 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 804 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
713 805 // management.
714 // management. 806 // DSP_IDLE3 is not supported in simulation
715 807 #else
716 // DSP_IDLE3 is not supported in simulation 808 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep
717 809 // management.
718 #else 810 // DSP_IDLE3 is not supported in simulation
719 #define W_A_DSP_IDLE3 0 811 #endif // CHIPSET 12
720 #endif 812 #else
813 #define W_A_DSP_IDLE3 0
814 #endif
815
816 #define W_A_DSP_PR20037 1
721 817
722 // DSP software work-around config 818 // DSP software work-around config
723 // bit0 - Work-around to support CRTG. 819 // bit0 - Work-around to support CRTG.
724 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 820 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
725 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 821 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
726 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 822 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
727 #if (ANALOG == 1) // OMEGA / NAUSICA 823 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
728 #define C_DSP_SW_WORK_AROUND 0x0006 824 #define C_DSP_SW_WORK_AROUND 0x0006
729 825
730 #elif (ANALOG == 2) // IOTA 826 #elif (ANLG_FAM == 2) // IOTA
731 #define C_DSP_SW_WORK_AROUND 0x000E 827 #define C_DSP_SW_WORK_AROUND 0x000E
732 828
733 #elif (ANALOG == 3) // SYREN 829 #elif (ANLG_FAM == 3) // SYREN
734 #define C_DSP_SW_WORK_AROUND 0x000E 830 #define C_DSP_SW_WORK_AROUND 0x000E
735 831
736 #endif 832 #endif
737 833
738 /* DSP debug trace configuration */ 834 /* DSP debug trace configuration */
739 /*-------------------------------*/ 835 /*-------------------------------*/
740 #if (MELODY_E2) 836 #if (MELODY_E2)
741 // In case of the melody E2 the DSP trace must be disable because the 837 // In case of the melody E2 the DSP trace must be disable because the
742 // melody instrument waves are overlayed with DSP trace buffer 838 // melody instrument waves are overlayed with DSP trace buffer
743 839
744 // DSP debug trace API buufer config 840 // DSP debug trace API buffer config
745 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 841 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
746 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 842 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
747 843
748 // DSP debug trace type config 844 // DSP debug trace type config
749 // |<-------------- Features -------------->|<---------- Levels ----------->| 845 // |<-------------- Features -------------->|<---------- Levels ----------->|
753 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 849 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
754 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 850 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
755 // Currently not supported ! 851 // Currently not supported !
756 #endif 852 #endif
757 #else 853 #else
758 // DSP debug trace API buufer config 854 // DSP debug trace API buffer config
759 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 855 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
760 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 856 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
761 857
762 // DSP debug trace type config 858 // DSP debug trace type config
763 // |<-------------- Features -------------->|<---------- Levels ----------->| 859 // |<-------------- Features -------------->|<---------- Levels ----------->|
764 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 860 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
765 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst. 861 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
766 862
767 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 863 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
768 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 864 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
769 #endif 865 #endif
770 866
771 // AMR trace 867 // AMR trace
772 #define C_AMR_TRACE_ID 55 868 #define C_AMR_TRACE_ID 55
773 869
777 873
778 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 874 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
779 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 875 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
780 876
781 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 877 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
782 #define DSP_DEBUG_GSM_MASK 0x08BD 878 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
783 #define DSP_DEBUG_GPRS_MASK 0x0f3d 879 #define DSP_DEBUG_GPRS_MASK 0x0f3d
784 #endif 880 #endif
785 #elif (DSP == 36) // ROM Code GPRS AMR. 881 #elif (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) // ROM Code GPRS AMR.
882
883 #if ((L1_PCM_EXTRACTION) && (SPEECH_RECO))
884 #error "PCM extraction and Speech recognition not supported simultaneously"
885 #endif
886
786 #define CLKMOD1 0x4006 // ... 887 #define CLKMOD1 0x4006 // ...
787 #define CLKMOD2 0x4116 // ...65 Mips pll free 888 #define CLKMOD2 0x4116 // ...65 Mips pll free
788 #define CLKSTART 0x29 // ...65 Mips 889 #define CLKSTART 0x29 // ...65 Mips
789 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 890 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
790 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 891 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
791 #define AEC 1 // AEC/NS not supported. 892 #define AEC 0 // AEC/NS not supported.
792 #if (OP_RIV_AUDIO == 0)
793 #define L1_NEW_AEC 1
794 #else
795 // Available but not yet tuned with Riviera AUDIO
796 #define L1_NEW_AEC 0 893 #define L1_NEW_AEC 0
797 #endif 894
798 #if ((L1_NEW_AEC) && (!AEC)) 895 #if ((L1_NEW_AEC) && (!AEC))
799 // First undef the flag to avoid warnings at compilation time 896 // First undef the flag to avoid warnings at compilation time
800 #undef AEC 897 #undef AEC
801 #define AEC 1 898 #define AEC 1
802 #endif 899 #endif
803 #define MAP 3 900 #define MAP 3
804 #undef L1_AMR_NSYNC 901 #undef L1_AMR_NSYNC
805 #define L1_AMR_NSYNC 1 902 #define L1_AMR_NSYNC 1
806 #define FF_L1_TCH_VOCODER_CONTROL 1 903 #define FF_L1_TCH_VOCODER_CONTROL 1
807 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 904 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
808 905
809 #define DSP_START 0x7000 906 #define DSP_START 0x7000
810 907
811 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer 908 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
812 909
813 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 910 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
814 #define ULYSSE 0 911 #define ULYSSE 0
815 912
816 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 913 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
817 914
818 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) 915 #if (CODE_VERSION == NOT_SIMULATION)
819 916 #if ((CHIPSET != 12) && (CHIPSET != 15))
820 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 917 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
821 918 // management.
822 // management. 919 // DSP_IDLE3 is not supported in simulation
823 920 #else // CHIPSET 12
824 // DSP_IDLE3 is not supported in simulation 921 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep
825 922 // management.
826 #else 923 // DSP_IDLE3 is not supported in simulation
924 #endif // CHIPSET 12
925 #else // CODE_VERSION
827 #define W_A_DSP_IDLE3 0 926 #define W_A_DSP_IDLE3 0
828 #endif 927 #endif
928
929 #define W_A_DSP_PR20037 1
829 930
830 // DSP software work-around config 931 // DSP software work-around config
831 // bit0 - Work-around to support CRTG. 932 // bit0 - Work-around to support CRTG.
832 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 933 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
833 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 934 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
834 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 935 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
835 #if (ANALOG == 1) // OMEGA / NAUSICA 936 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
836 #define C_DSP_SW_WORK_AROUND 0x0006 937 #define C_DSP_SW_WORK_AROUND 0x0006
837 938
838 #elif (ANALOG == 2) // IOTA 939 #elif (ANLG_FAM == 2) // IOTA
839 #define C_DSP_SW_WORK_AROUND 0x000E 940 #define C_DSP_SW_WORK_AROUND 0x000E
840 941
841 #elif (ANALOG == 3) // SYREN 942 #elif (ANLG_FAM == 3) // SYREN
842 #define C_DSP_SW_WORK_AROUND 0x000E 943 #define C_DSP_SW_WORK_AROUND 0x000E
843 #endif 944
844 945 #elif (ANLG_FAM == 11) // TRITON
845 // This workaround should be enabled only for H2-sample on full build config 946 #define C_DSP_SW_WORK_AROUND 0x000E
846 #if (OP_L1_STANDALONE==1) 947
847 #define RAZ_VULSWITCH_REGAUDIO 0
848 #endif 948 #endif
849 949
850 /* DSP debug trace configuration */ 950 /* DSP debug trace configuration */
851 /*-------------------------------*/ 951 /*-------------------------------*/
852 #if (MELODY_E2) 952 // Note:
853 // In case of the melody E2 the DSP trace must be disable because the 953 // In case of melody E2, MP3, AAC or Dyn Dwnld ACTIVITY the DSP trace is automatically disabled
854 // melody instrument waves are overlayed with DSP trace buffer 954 // because the melody instrument waves are overlayed with DSP trace buffer (supported since patch 7c20)
855 955
856 // DSP debug trace API buufer config 956 // DSP debug trace API buffer config
857 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 957 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
858 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 958 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
859 959
860 // DSP debug trace type config 960 // DSP debug trace type config
861 // |<-------------- Features -------------->|<---------- Levels ----------->| 961 // |<-------------- Features -------------->|<---------- Levels ----------->|
862 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 962 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
863 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. 963
964 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)// C_DEBUG_TRACE_TYPE 0x0012 changed from 0x0054 for DSP load reduce
965 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
966 #else
967 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
968 #endif
969
864 970
865 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 971 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
866 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 972 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
867 // Currently not supported ! 973 // Currently not supported !
868 #endif 974 #endif
869 #else
870 // DSP debug trace API buufer config
871 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
872 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
873
874 // DSP debug trace type config
875 // |<-------------- Features -------------->|<---------- Levels ----------->|
876 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
877 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
878
879 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
880 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
881 #endif
882 975
883 // AMR trace 976 // AMR trace
884 #define C_AMR_TRACE_ID 55 977 #define C_AMR_TRACE_ID 55
885 978
886 #endif 979
887 /* d_error_status */ 980 /* d_error_status */
888 /*-------------------------------*/ 981 /*-------------------------------*/
889 982
890 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 983 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
891 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 984 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
892 985
893 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 986 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
894 #define DSP_DEBUG_GSM_MASK 0x08BD 987 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
895 #define DSP_DEBUG_GPRS_MASK 0x0f3d 988 #define DSP_DEBUG_GPRS_MASK 0x0f3d
896 #endif 989 #endif
897 #endif // DSP 990 #endif // DSP
898 991
899 /*------------------------------------*/ 992 /*------------------------------------*/
944 #define L1_AMR_NSYNC 0 1037 #define L1_AMR_NSYNC 0
945 #endif 1038 #endif
946 1039
947 #ifndef FF_L1_TCH_VOCODER_CONTROL 1040 #ifndef FF_L1_TCH_VOCODER_CONTROL
948 #define FF_L1_TCH_VOCODER_CONTROL 0 1041 #define FF_L1_TCH_VOCODER_CONTROL 0
949 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 1042 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
950 #endif 1043 #define W_A_DSP_PR20037 0
1044 #endif
1045
951 1046
952 /*------------------------------------*/ 1047 /*------------------------------------*/
953 /* Download */ 1048 /* Download */
954 /*------------------------------------*/ 1049 /*------------------------------------*/
955 1050
977 #define PATCH_DSP_DWNLD 3 1072 #define PATCH_DSP_DWNLD 3
978 1073
979 // MAC-S status reporting to Layer 1 1074 // MAC-S status reporting to Layer 1
980 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1 1075 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
981 1076
982
983 // Possible choice for dll_dcch_downlink interface (with FN or without FN) 1077 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
984 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */ 1078 #define SEND_FN_TO_L2_IN_DCCH 0
1079
1080
1081 #define L1_CHECK_COMPATIBLE 1 //Check L1A message compatiblity
1082
985 1083
986 //--------------------------------------------------------------------------------- 1084 //---------------------------------------------------------------------------------
987 1085
988 // Neighbor Cell RXLEV indication
989 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
990 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
991 #else
992 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
993 #endif
994
995 #endif /* __L1_CONFG_H__ */ 1086 #endif /* __L1_CONFG_H__ */