--- a/gsm-fw/L1/include/l1_confg.h	Tue Jul 15 22:19:53 2014 +0000
+++ b/gsm-fw/L1/include/l1_confg.h	Fri Aug 01 16:38:35 2014 +0000
@@ -3,13 +3,22 @@
  * L1_CONFG.H
  *
  *        Filename l1_confg.h
- *  Copyright 2003 (C) Texas Instruments  
+ *  Copyright 2003 (C) Texas Instruments
  *
  ************* Revision Controle System Header *************/
 
 #ifndef __L1_CONFG_H__
 #define __L1_CONFG_H__
 
+#ifndef _WINDOWS
+#include "l1sw.cfg"    // Configuration Software
+#include "board.cfg"
+#include "chipset.cfg"
+#include "rf.cfg"
+#include "swconfig.cfg"
+#include "sys.cfg"
+#endif
+
 // Traces...
 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
@@ -32,7 +41,7 @@
 #define SIMULATION     1
 #define NOT_SIMULATION 2
 
-// RCL functions Version possible choices
+// RLC functions Version possible choices
 //------------------------------
 #define       POLL_FORCED     0
 #define       RLC_SCENARIO    1
@@ -40,64 +49,60 @@
 
 // possible choices for UART trace output
 //------------------------------
-#define       MODEM_UART     0
-#define       IRDA_UART      1
-#if (CHIPSET == 12)
-  #define     MODEM2_UART    2
+#if (CHIPSET != 15)
+  #define       MODEM_UART     0
+  #define       IRDA_UART      1
+  #if (CHIPSET == 12)
+    #define     MODEM2_UART    2
+  #endif
+#else
+  // There is only one UART in Locosto
+  #define       MODEM_UART     0
 #endif
 
 //============
 // CODE CHOICE
 //============
-#if 0
 #if (OP_L1_STANDALONE==0)
 #define CODE_VERSION NOT_SIMULATION
 #else // OP_L1_STANDALONE
 #ifdef WIN32
-#define CODE_VERSION  SIMULATION
+  #define CODE_VERSION  SIMULATION
 #else // WIN32
-#define CODE_VERSION  NOT_SIMULATION
+  #define CODE_VERSION  NOT_SIMULATION
 #endif // WIN32
 #endif // OP_L1_STANDALONE
-#endif // #if 0
-
-/* FreeCalypso */
-#define	CODE_VERSION	NOT_SIMULATION
-#define	AMR		1
-#define	L1_12NEIGH	1
-#define	L1_DYN_DSP_DWNLD	0	/* for now */
-#define	L1_EOTD		0
-#define	L1_GTT		0
-#define	ORDER2_TX_TEMP_CAL	1
-#define	TRACE_TYPE	4
-#define	VCXO_ALGO	1
-
-/* TESTMODE will be enabled with feature l1tm */
-
-#if CONFIG_AUDIO
-#  define AUDIO_TASK	1  // Enable the L1 audio features
-#  define MELODY_E2	1
-#endif
-
-#if CONFIG_GPRS
-#  define L1_GPRS	1
-#else
-#  define L1_GPRS	0
-#endif
-
 //---------------------------------------------------------------------------------
 // Test with full simulation.
 //---------------------------------------------------------------------------------
 #if (CODE_VERSION == SIMULATION)
 
+
+  #undef FF_L1_IT_DSP_USF
+  #define FF_L1_IT_DSP_USF       0
+  #undef FF_L1_IT_DSP_DTX
+#if (AMR == 1)
+  #define FF_L1_IT_DSP_DTX     1 //it should be 1, sajal- temp made it 0 for build purpose
+#else
+  #define FF_L1_IT_DSP_DTX     0
+#endif
+
+  #define L1_DRP_IQ_SCALING    0
+
   // Test Scenari...
   #define SCENARIO_FILE          1  // Test Scenario comes from input files.
   #define SCENARIO_MEM           0  // Test Scenario comes from RAM.
 
+  // In Simulation AUDIO_DEBUG Should be 0
+  #define AUDIO_DEBUG 0
+
   // Traces...
   #undef TRACE_TYPE
   #define TRACE_TYPE             5
   #define LOGFILE_TRACE          1  // trace in an output logfile
+
+  #define BURST_PARAM_LOG_ENABLE 0  // Burst Param Log Enable
+
   #define FLOWCHART              0  // Message sequence/flow chart trace.
   #define NUCLEUS_TRACE          0  // Nucleus error trace
   #define EOTD_TRACE             1  // EOTD log trace
@@ -107,11 +112,15 @@
 
   // Control algorithms...
   #define AFC_ALGO               1  // AFC algorithm.
+#if (L1_SAIC != 0)
+  #define TOA_ALGO               2  // TOA algorithm.
+#else
   #define TOA_ALGO               1  // TOA algorithm.
+#endif
   #define AGC_ALGO               1  // AGC algorithm.
   #define TA_ALGO                0  // TA (Timing Advance) algorithm.
   #undef VCXO_ALGO
-  #define VCXO_ALGO              0  // VCXO algo
+  #define VCXO_ALGO              1  // VCXO algo
   #undef DCO_ALGO
   #define DCO_ALGO               0  // DCO algo (TIDE)
   #undef ORDER2_TX_TEMP_CAL
@@ -128,11 +137,11 @@
   #define AUDIO_L1_STANDALONE    0  // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
 
   #define GTT_SIMULATION         1  // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
-  #define TTY_SYNC_MCU           1  // TTY WORKAROUND BUG03401
-  #define TTY_SYNC_MCU_2         1  // 
+  #define TTY_SYNC_MCU           0  // TTY WORKAROUND BUG03401
+  #define TTY_SYNC_MCU_2         0  //
   #define L1_GTT_FIFO_TEST_ATOMIC 0 //
   #define NEW_WKA_PATCH          0
-  #define OPTIMISED              1
+  #define OPTIMISED              0
 
   #define L1_RECOVERY            0  // L1 recovery
 
@@ -156,12 +165,59 @@
 
   #undef OP_WCP
   #define OP_WCP                 0  // No WCP integration
+
+  #undef L1_DRP
+  #define L1_DRP                0  // L1 supporting DRP interface
+
+  #undef DRP_MEM_SIMULATION
+  #define DRP_MEM_SIMULATION          0
 //---------------------------------------------------------------------------------
 // Test with H/W platform.
 //---------------------------------------------------------------------------------
+
+  #if (GSM_IDLE_RAM == 1)
+    #define GSM_IDLE_RAM_DEBUG 0
+  #endif
+
+  #define AFC_BYPASS_MODE        0
+ #define PWMEAS_IF_MODE_FORCE  0
+// WA for OMAPS00099442 must be disabled in PC simulation
+  #undef L1_FF_WA_OMAPS00099442
+  #define L1_FF_WA_OMAPS00099442 0
+
 #elif (CODE_VERSION == NOT_SIMULATION)
 
-  #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1) 
+  #define L1_DRP_IQ_SCALING    1
+  // In Target AUDIO_DEBUG could be turned ON to debug any AUDIO ON/OFF issues
+  #define AUDIO_DEBUG 0
+
+  #if (GSM_IDLE_RAM == 1)
+    #if ((CHIPSET == 12) || (CHIPSET == 10))
+      #define GSM_IDLE_RAM_DEBUG 1
+    #else
+      #define GSM_IDLE_RAM_DEBUG 0
+    #endif
+  #else
+    #define GSM_IDLE_RAM_DEBUG 0
+  #endif
+
+#define L1_VPM  1
+  #if (OP_L1_STANDALONE == 1)
+    #if (CHIPSET == 15)
+      #if ((BOARD == 71) && (FLASH == 0))
+        // Not possible in I-SAMPLE only RAM configuration as there will
+        // not be enough memory space
+        #define BURST_PARAM_LOG_ENABLE  0
+      #else
+        #define BURST_PARAM_LOG_ENABLE  1
+      #endif
+    #else
+      #define BURST_PARAM_LOG_ENABLE  0
+    #endif
+  #else
+    #define BURST_PARAM_LOG_ENABLE  0
+  #endif
+
   // Work around about Calypso RevA: the bus is floating (Cf PB01435)
   // (corrected with Calypso ReV B and Calypso C035)
   #if (CHIPSET == 7)
@@ -170,16 +226,22 @@
     #define W_A_CALYPSO_BUG_01435 0
   #endif
 
+  #if (CHIPSET == 12) // Not needed for CHIPSET =15, as there is no extended page mode in Locosto
+    #define W_A_CALYPSO_PLUS_SPR_19599 1
+  #else
+    #define W_A_CALYPSO_PLUS_SPR_19599 0
+  #endif
 
   // for AMR thresolds definition CQ22226
-  #define AMR_THRESHOLDS_WORKAROUND 1
+  #define W_A_AMR_THRESHOLDS 1
+  #define W_A_PCTM_RX_AGC_GLOBAL_PARAMS 1 // For support of PCTM
 
   #if (L1_GTT==1)
-    #define TTY_SYNC_MCU 1
-    #define TTY_SYNC_MCU_2 1
+    #define TTY_SYNC_MCU 0
+    #define TTY_SYNC_MCU_2 0
     #define L1_GTT_FIFO_TEST_ATOMIC 0
     #define NEW_WKA_PATCH          0
-    #define OPTIMISED              1
+    #define OPTIMISED              0
   #else
     #define TTY_SYNC_MCU_2 0
     #define L1_GTT_FIFO_TEST_ATOMIC 0
@@ -188,7 +250,20 @@
     #define OPTIMISED              0
 
   #endif
- 
+
+  #undef FF_L1_IT_DSP_USF
+#if (L1_GPRS == 1)
+  #define FF_L1_IT_DSP_USF       1
+#else
+  #define FF_L1_IT_DSP_USF       0
+#endif
+  #undef FF_L1_IT_DSP_DTX
+#if (AMR == 1)
+  #define FF_L1_IT_DSP_DTX     1
+#else
+  #define FF_L1_IT_DSP_DTX     0
+#endif
+
   // Traces...
   #define NUCLEUS_TRACE        0  // Nucleus error trace
   #define FLOWCHART            0  // Message sequence/flow chart trace.
@@ -208,7 +283,11 @@
   // Control algorithms...
   #define AFC_ALGO               1  // AFC algorithm.
   //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
+#if (L1_SAIC != 0)
+  #define TOA_ALGO               2  // TOA algorithm.
+#else
   #define TOA_ALGO               1  // TOA algorithm.
+#endif
   #define AGC_ALGO               1  // AGC algorithm.
   #define TA_ALGO                1  // TA (Timing Advance) algorithm.
 
@@ -217,10 +296,7 @@
   #define ADC_TIMER_ON           0  // Timer for ADC measurements
   #define AFC_ON                 1  // Enable of the Omega AFC module
 
-#if 0
-  /* FreeCalypso: moved to config section above */
   #define AUDIO_TASK             1  // Enable the L1 audio features
-#endif
   #define AUDIO_SIMULATION       0  // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
   #if (OP_L1_STANDALONE == 1)
     #define AUDIO_L1_STANDALONE    1  // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
@@ -230,10 +306,16 @@
 
   #define GTT_SIMULATION         0  // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
 
-  #define OP_BT                  0  // Simulation of ISLAND (BLUETOOTH) sleep management 
+  #define OP_BT                  0  // Simulation of ISLAND (BLUETOOTH) sleep management
 
   #define L1_RECOVERY            1  // L1 recovery
 
+  #if ((RF_FAM == 60) || (RF_FAM == 61))
+    #define L1_DRP                 1  // L1 supporting DRP interface
+  #else
+    #define L1_DRP                 0  // L1 supporting DRP interface
+  #endif
+  #define DRP_MEM_SIMULATION   0 // DRP memory simulation OFF by default
 
   #if (L1_GPRS == 1)
     #define RLC_VERSION            RLC_SCENARIO
@@ -259,6 +341,16 @@
     #define DSP_BACKGROUND_TASKS     0
     #define RLC_DL_BLOCK_STAT        0  // Default value; Never change it
   #endif
+#define PWMEAS_IF_MODE_FORCE  1
+// WA for OMAPS00099442 (OMAPS0010023 (N12.x), OMAPS000010022 (N5.x))
+  // The problem is: When NW is lost due to reception gap or cell border range,
+  // the MS will try to re-synchronize on the cell with the TPU timing aligned
+  // with the timing of the cell. So the FB will start within the 92 bits of the TPU window and
+  // will be missed. This issue is due to a limitation of the legacy FB demodulation algorithm
+  // WA is to re-initialize the TPU with an arbitrary timing value
+  #undef L1_FF_WA_OMAPS00099442
+  #define L1_FF_WA_OMAPS00099442 1
+
 #endif
 
 // Audio tasks selection
@@ -271,48 +363,52 @@
   #if (OP_L1_STANDALONE == 1)
     #define GSMLITE 1
   #endif
+  #if (CODE_VERSION == SIMULATION)
+    #define L1_VOICE_MEMO       1
+  #endif
   #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
     #define MELODY_E1        1  // Enable melody format E1 feature
-    #define VOICE_MEMO       1  // Enable voice memorization feature
 
+    #if(L1_VOICE_MEMO == 1)
+      #define VOICE_MEMO       1  // Enable voice memorization feature
+    #else
+      #define VOICE_MEMO       0
+    #endif
     #define FIR              1  // Enable FIR feature
-    #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+    #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
       #define AUDIO_MODE       1  // Enable Audio mode feature
     #else
       #define AUDIO_MODE        0  // Disable Audio mode feature
     #endif
   #else
     #define MELODY_E1        0  // Disable melody format E1 feature
-    #define VOICE_MEMO       0  // Disable voice memorization feature
+    #if(L1_VOICE_MEMO == 1)
+      #define VOICE_MEMO       1  // Enable voice memorization feature
+    #else
+      #define VOICE_MEMO       0
+    #endif
     #if (MELODY_E2)
-	    #define FIR              1  // Enable FIR feature  
-	  #else
-      #define FIR              0  // Disable FIR feature  
+      #define FIR            1  // Enable FIR feature
+    #else
+      #define FIR            0  // Disable FIR feature
     #endif
-
     #define AUDIO_MODE       0  // Disable Audio mode feature
   #endif
-  // Define CPORT for ESample only
-  #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36))) 
-    #define L1_CPORT         1  // Enable cport feature
-  #else
-    #define L1_CPORT         0  // Disable cport feature
-  #endif
+
 
 #else
   #define KEYBEEP           0  // Enable keybeep feature
   #define TONE              0  // Enable tone feature
   #define MELODY_E1         0  // Enable melody format E1 feature
-  #define VOICE_MEMO        0  // Enable voice memorization feature
-
+  #define VOICE_MEMO        0 // Enable voice memorization feature
   #define FIR               0  // Enable FIR feature
   #define AUDIO_MODE        0  // Enable Audio mode feature
-  #define L1_CPORT          0  // Enable cport feature
 #endif
+#define L1_MIDI_BUFFER 1
 
 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
 #if (OP_RIV_AUDIO == 1)
-  #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
+  #define L1_AUDIO_DRIVER (L1_VOICE_MEMO_AMR | L1_EXT_AUDIO_MGT | L1_MP3) // Riviera audio driver (only Voice Memo AMR is available)
 #endif
 
 
@@ -326,6 +422,7 @@
 
 // Standard (frequency plan) selections
 //-------------------------------------
+#if(L1_FF_MULTIBAND == 0) // std id is not used if multiband feature is enabled
 
 #define GSM             1            // GSM900.
 #define GSM_E           2            // GSM900 Extended.
@@ -336,12 +433,27 @@
 #define GSM850          7            // GSM850 Band
 #define DUAL_US         8            // PCS1900 + GSM850
 
+#endif // L1_FF_MULTIBAND
+
 /*------------------------------------*/
 /* Power Management                   */
 /*------------------------------------*/
 #define PWR_MNGT  1            // POWER management active if l1_config.pwr_mngt=1
 
-
+/*------------------------------------*/
+/*    BT Audio                        */ 
+/*------------------------------------*/
+#if ((L1_MP3 == 1) || (L1_AAC == 1))
+#if (OP_L1_STANDALONE == 0)
+#if((PSP_STANDALONE == 1) || (DRP_FW_BUILD == 1))
+#define L1_BT_AUDIO 0
+#else
+#define L1_BT_AUDIO 1
+#endif
+#else
+#define L1_BT_AUDIO 0
+#endif
+#endif
 /*---------------------------------------------------------------------------*/
 /* DSP configurations                                                        */
 /* ------------------                                                        */
@@ -402,11 +514,11 @@
     // In case of the melody E2 the DSP trace must be disable because the
     // melody instrument waves are overlayed with DSP trace buffer
 
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
   #else
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
   #endif
@@ -469,12 +581,8 @@
   #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
   #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
   #define AEC        1         // AEC/NS not supported.
-  #if (OP_RIV_AUDIO == 0)
-    #define L1_NEW_AEC 1
-  #else
-  // Available but not yet tuned with Riviera AUDIO    
-  #define L1_NEW_AEC 0
-  #endif
+  #define L1_NEW_AEC 1
+
   #if ((L1_NEW_AEC) && (!AEC))
     // First undef the flag to avoid warnings at compilation time
     #undef AEC
@@ -492,14 +600,10 @@
 
   #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
 
-  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
-
+  #if (CODE_VERSION == NOT_SIMULATION)
     #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
-
                                 // management.
-
-								// DSP_IDLE3 is not supported in simulation
-
+                // DSP_IDLE3 is not supported in simulation
   #else
     #define W_A_DSP_IDLE3 0
   #endif
@@ -510,13 +614,13 @@
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
 
-  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANALOG == 2)  // IOTA
+  #elif  (ANLG_FAM == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANALOG == 3)  // SYREN
+  #elif  (ANLG_FAM == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -527,7 +631,7 @@
     // In case of the melody E2 the DSP trace must be disable because the
     // melody instrument waves are overlayed with DSP trace buffer
 
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
 
@@ -541,7 +645,7 @@
                                                 // Currently not supported !
     #endif
   #else
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
 
@@ -551,7 +655,7 @@
     #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
 
     #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
-    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
     #endif
   #endif
   /* d_error_status                */
@@ -561,7 +665,7 @@
     #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
 
     // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
-    #define DSP_DEBUG_GSM_MASK     0x0000
+    #define DSP_DEBUG_GSM_MASK     0x08BD // L1_MCU-SPR-15852
     #define DSP_DEBUG_GPRS_MASK    0x0f3d
   #endif
 
@@ -577,12 +681,8 @@
   #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
   #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
   #define AEC        1         // AEC/NS not supported.
-  #if (OP_RIV_AUDIO == 0)
-    #define L1_NEW_AEC 1
-  #else
-  // Available but not yet tuned with Riviera AUDIO    
-    #define L1_NEW_AEC 0
-   #endif
+  #define L1_NEW_AEC 1
+
   #if ((L1_NEW_AEC) && (!AEC))
     // First undef the flag to avoid warnings at compilation time
     #undef AEC
@@ -599,14 +699,10 @@
 
   #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
 
-  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
-
-    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
-
-                                // management.
-
-								// DSP_IDLE3 is not supported in simulation
-
+  #if (CODE_VERSION == NOT_SIMULATION)
+  #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+                              // management.
+                // DSP_IDLE3 is not supported in simulation
   #else
     #define W_A_DSP_IDLE3 0
   #endif
@@ -616,13 +712,13 @@
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANALOG == 2)  // IOTA
+  #elif  (ANLG_FAM == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANALOG == 3)  // SYREN
+  #elif  (ANLG_FAM == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -633,7 +729,7 @@
     // In case of the melody E2 the DSP trace must be disable because the
     // melody instrument waves are overlayed with DSP trace buffer
 
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
 
@@ -647,7 +743,7 @@
                                                 // Currently not supported !
     #endif
   #else
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
 
@@ -657,7 +753,7 @@
     #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
 
     #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
-    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
     #endif
 
     // AMR trace
@@ -670,8 +766,8 @@
   #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
     #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
 
-    // masks to apply on d_error_status bit field
-    #define DSP_DEBUG_GSM_MASK     0x0000
+    // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
+    #define DSP_DEBUG_GSM_MASK     0x08BD // L1_MCU-SPR-15852
     #define DSP_DEBUG_GPRS_MASK    0x0f3d
   #endif
 
@@ -682,12 +778,8 @@
   #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
   #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
   #define AEC        1         // AEC/NS not supported.
-  #if (OP_RIV_AUDIO == 0)
-    #define L1_NEW_AEC 1
-  #else
-  // Available but not yet tuned with Riviera AUDIO    
-    #define L1_NEW_AEC 0
-  #endif
+  #define L1_NEW_AEC 1
+
   #if ((L1_NEW_AEC) && (!AEC))
     // First undef the flag to avoid warnings at compilation time
     #undef AEC
@@ -696,7 +788,7 @@
   #define MAP        3
 
   #define FF_L1_TCH_VOCODER_CONTROL 1
-  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
+  #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
 
   #define DSP_START  0x7000
 
@@ -707,30 +799,34 @@
 
   #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
 
-  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
-
-    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
-
-                                // management.
+  #if (CODE_VERSION == NOT_SIMULATION)
+    #if (CHIPSET != 12)
+        #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+                                    // management.
+                                    // DSP_IDLE3 is not supported in simulation
+    #else
+      #define W_A_DSP_IDLE3 0     // Work around to report DSP state to the ARM for Deep Sleep
+                                  // management.
+                                  // DSP_IDLE3 is not supported in simulation
+    #endif // CHIPSET 12
+  #else
+      #define W_A_DSP_IDLE3 0
+  #endif
 
-								// DSP_IDLE3 is not supported in simulation
-
-  #else
-    #define W_A_DSP_IDLE3 0
-  #endif
+  #define W_A_DSP_PR20037 1
 
   // DSP software work-around config
   //  bit0 - Work-around to support CRTG.
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANALOG == 2)  // IOTA
+  #elif  (ANLG_FAM == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANALOG == 3)  // SYREN
+  #elif  (ANLG_FAM == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -741,7 +837,7 @@
     // In case of the melody E2 the DSP trace must be disable because the
     // melody instrument waves are overlayed with DSP trace buffer
 
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
 
@@ -755,7 +851,7 @@
                                                 // Currently not supported !
     #endif
   #else
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
     #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
 
@@ -765,7 +861,7 @@
     #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Timer + Buffer Header + Burst.
 
     #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
-    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
     #endif
 
     // AMR trace
@@ -779,22 +875,23 @@
     #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
 
     // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
-    #define DSP_DEBUG_GSM_MASK     0x08BD
+    #define DSP_DEBUG_GSM_MASK     0x08BD // L1_MCU-SPR-15852
     #define DSP_DEBUG_GPRS_MASK    0x0f3d
   #endif
-#elif (DSP == 36)            // ROM Code GPRS AMR.
+#elif (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)      // ROM Code GPRS AMR.
+
+  #if ((L1_PCM_EXTRACTION) && (SPEECH_RECO))
+    #error "PCM extraction and Speech recognition not supported simultaneously"
+  #endif
+
   #define CLKMOD1    0x4006  // ...
   #define CLKMOD2    0x4116  // ...65 Mips pll free
   #define CLKSTART   0x29    // ...65 Mips
   #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
   #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
-  #define AEC        1         // AEC/NS not supported.
-  #if (OP_RIV_AUDIO == 0)
-    #define L1_NEW_AEC 1
-  #else
-  // Available but not yet tuned with Riviera AUDIO    
+  #define AEC        0         // AEC/NS not supported.
     #define L1_NEW_AEC 0
-  #endif
+
   #if ((L1_NEW_AEC) && (!AEC))
     // First undef the flag to avoid warnings at compilation time
     #undef AEC
@@ -804,7 +901,7 @@
   #undef  L1_AMR_NSYNC
   #define L1_AMR_NSYNC 1
   #define FF_L1_TCH_VOCODER_CONTROL 1
-  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
+  #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
 
   #define DSP_START  0x7000
 
@@ -815,75 +912,71 @@
 
   #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
 
-  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
-
-    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
-
-                                // management.
-
-								// DSP_IDLE3 is not supported in simulation
-
-  #else
+  #if (CODE_VERSION == NOT_SIMULATION)
+    #if ((CHIPSET != 12) && (CHIPSET != 15))
+      #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+                                  // management.
+                                  // DSP_IDLE3 is not supported in simulation
+    #else  // CHIPSET 12
+      #define W_A_DSP_IDLE3 0     // Work around to report DSP state to the ARM for Deep Sleep
+                                  // management.
+                                  // DSP_IDLE3 is not supported in simulation
+    #endif // CHIPSET 12
+  #else // CODE_VERSION
     #define W_A_DSP_IDLE3 0
   #endif
 
+  #define W_A_DSP_PR20037 1
+
   // DSP software work-around config
   //  bit0 - Work-around to support CRTG.
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANALOG == 2)  // IOTA
+  #elif  (ANLG_FAM == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANALOG == 3)  // SYREN
+  #elif  (ANLG_FAM == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
-  #endif
 
-  // This workaround should be enabled only for H2-sample on full build config
-  #if (OP_L1_STANDALONE==1)
-    #define RAZ_VULSWITCH_REGAUDIO 0
+  #elif  (ANLG_FAM == 11)  // TRITON
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
   #endif
 
   /* DSP debug trace configuration */
   /*-------------------------------*/
-  #if (MELODY_E2)
-    // In case of the melody E2 the DSP trace must be disable because the
-    // melody instrument waves are overlayed with DSP trace buffer
+   // Note:
+  // In case of melody E2, MP3, AAC or Dyn Dwnld ACTIVITY the DSP trace is automatically disabled
+  // because the melody instrument waves are overlayed with DSP trace buffer (supported since patch 7c20)
 
-    // DSP debug trace API buufer config
+    // DSP debug trace API buffer config
     #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
-    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+    #define C_DEBUG_BUFFER_SIZE 2047       // Real size is incremented by 1 for DSP write pointer.
 
     // DSP debug trace type config
     //             |<-------------- Features -------------->|<---------- Levels ----------->|
     // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
-    #define C_DEBUG_TRACE_TYPE  0x0000  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)// C_DEBUG_TRACE_TYPE  0x0012 changed from 0x0054 for DSP load reduce
+      #define C_DEBUG_TRACE_TYPE  0x0012  // Level = KERNEL; Features = Timer, Burst, Buffer Header.
+    #else
+      #define C_DEBUG_TRACE_TYPE  0x0000  // Level = KERNEL; Features = Timer, Burst, Buffer Header.
+    #endif
+
 
     #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
       #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability
                                                 // Currently not supported !
     #endif
-  #else
-    // DSP debug trace API buufer config
-    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
-    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
-
-    // DSP debug trace type config
-    //             |<-------------- Features -------------->|<---------- Levels ----------->|
-    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
-    #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
-
-    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
-    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
-    #endif
 
     // AMR trace
     #define C_AMR_TRACE_ID 55
 
-  #endif
+
   /* d_error_status                */
   /*-------------------------------*/
 
@@ -891,7 +984,7 @@
     #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
 
     // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
-    #define DSP_DEBUG_GSM_MASK     0x08BD
+    #define DSP_DEBUG_GSM_MASK     0x08BD // L1_MCU-SPR-15852
     #define DSP_DEBUG_GPRS_MASK    0x0f3d
   #endif
 #endif // DSP
@@ -946,9 +1039,11 @@
 
 #ifndef FF_L1_TCH_VOCODER_CONTROL
   #define FF_L1_TCH_VOCODER_CONTROL 0
-  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 
+  #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
+  #define W_A_DSP_PR20037 0
 #endif
 
+
 /*------------------------------------*/
 /* Download                           */
 /*------------------------------------*/
@@ -979,17 +1074,13 @@
 // MAC-S status reporting to Layer 1
 #define MACS_STATUS     0   // MAC-S STATUS activated if set to 1
 
+// Possible choice for dll_dcch_downlink interface (with FN or without FN)
+#define SEND_FN_TO_L2_IN_DCCH 0
 
-// Possible choice for dll_dcch_downlink interface (with FN or without FN)
-#define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
+
+#define L1_CHECK_COMPATIBLE 1    //Check L1A message compatiblity
+
 
 //---------------------------------------------------------------------------------
 
-// Neighbor Cell RXLEV indication
-#if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
- #define  L1_MPHC_RXLEV_IND_REPORT_SORT 1
-#else
- #define  L1_MPHC_RXLEV_IND_REPORT_SORT 0
-#endif
-
 #endif /* __L1_CONFG_H__ */