FreeCalypso > hg > freecalypso-sw
comparison gsm-fw/L1/cust0/l1_rf35.h @ 152:26472940e5b0
l1_rf<N>.h headers preened
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 17 Nov 2013 04:59:55 +0000 |
parents | d0de2d0a426d |
children |
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151:d0de2d0a426d | 152:26472940e5b0 |
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25 | 25 |
26 /******************************************************/ | 26 /******************************************************/ |
27 /* TXPWR configuration... */ | 27 /* TXPWR configuration... */ |
28 /* Fixed TXPWR value when GSM management is disabled. */ | 28 /* Fixed TXPWR value when GSM management is disabled. */ |
29 /******************************************************/ | 29 /******************************************************/ |
30 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) | 30 #if ((ANALOG == 1) || (ANALOG == 2)) |
31 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252 | 31 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252 |
32 // #define FIXED_TXPWR 0x0a12 // TXPWR=15, value=40 | 32 // #define FIXED_TXPWR 0x0a12 // TXPWR=15, value=40 |
33 #define FIXED_TXPWR 0x1a12 // TXPWR=15, EVA4, CRTP1 | 33 #define FIXED_TXPWR 0x1a12 // TXPWR=15, EVA4, CRTP1 |
34 #endif | 34 #endif |
35 | 35 |
38 /* ANALOG delay (in qbits) */ | 38 /* ANALOG delay (in qbits) */ |
39 /************************************/ | 39 /************************************/ |
40 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal | 40 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal |
41 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block | 41 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block |
42 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block | 42 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block |
43 #if (ANLG_FAM == 1) | 43 #if (ANALOG == 1) |
44 #define UL_ABB_DELAY 6 // modulator input to output delay | 44 #define UL_ABB_DELAY 6 // modulator input to output delay |
45 #endif | 45 #endif |
46 #if (ANLG_FAM == 2) | 46 #if (ANALOG == 2) |
47 #define UL_ABB_DELAY 3 // modulator input to output delay | 47 #define UL_ABB_DELAY 3 // modulator input to output delay |
48 #endif | 48 #endif |
49 | 49 |
50 /************************************/ | 50 /************************************/ |
51 /* TX Propagation delay... */ | 51 /* TX Propagation delay... */ |
52 /************************************/ | 52 /************************************/ |
53 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) | 53 #if ((ANALOG == 1) || (ANALOG == 2)) |
54 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 + NB_MARGIN | 54 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 + NB_MARGIN |
55 #endif | 55 #endif |
56 | 56 |
57 /************************************/ | 57 /************************************/ |
58 /* Initial value for APC DELAY */ | 58 /* Initial value for APC DELAY */ |
59 /************************************/ | 59 /************************************/ |
60 #if (ANLG_FAM == 1) | 60 #if (ANALOG == 1) |
61 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 | 61 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
62 #define APCDEL_DOWN 2 // minimum value: 2 | 62 #define APCDEL_DOWN 2 // minimum value: 2 |
63 #define APCDEL_UP (6+5) // minimum value: 6 | 63 #define APCDEL_UP (6+5) // minimum value: 6 |
64 #endif | 64 #endif |
65 #if (ANLG_FAM == 2) | 65 #if (ANALOG == 2) |
66 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 | 66 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
67 #define APCDEL_DOWN 2 // minimum value: 2 | 67 #define APCDEL_DOWN 2 // minimum value: 2 |
68 #define APCDEL_UP (6+2) // minimum value: 6 | 68 #define APCDEL_UP (6+2) // minimum value: 6 |
69 #endif | 69 #endif |
70 | 70 |
80 // hisr() in the first wake-up frame !!!! | 80 // hisr() in the first wake-up frame !!!! |
81 | 81 |
82 /************************************/ | 82 /************************************/ |
83 /* Baseband registers */ | 83 /* Baseband registers */ |
84 /************************************/ | 84 /************************************/ |
85 #if (ANLG_FAM == 1) | 85 #if (ANALOG == 1) |
86 // Omega registers values will be programmed at 1st DSP communication interrupt | 86 // Omega registers values will be programmed at 1st DSP communication interrupt |
87 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG | 87 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG |
88 #define C_AFCCTLADD 0x002a | TRUE // Value at reset | 88 #define C_AFCCTLADD 0x002a | TRUE // Value at reset |
89 #define C_VBUCTRL 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute | 89 #define C_VBUCTRL 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute |
90 #define C_VBDCTRL 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB | 90 #define C_VBDCTRL 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB |
97 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1 | 97 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
98 // BULRUDEL will be initialized on rach only .... | 98 // BULRUDEL will be initialized on rach only .... |
99 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) | 99 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) |
100 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' | 100 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' |
101 #endif | 101 #endif |
102 #if (ANLG_FAM == 2) | 102 #if (ANALOG == 2) |
103 // IOTA registers values will be programmed at 1st DSP communication interrupt | 103 // IOTA registers values will be programmed at 1st DSP communication interrupt |
104 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG | 104 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
105 #define C_AFCCTLADD 0x002a | TRUE // Value at reset | 105 #define C_AFCCTLADD 0x002a | TRUE // Value at reset |
106 #define C_VBUCTRL 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB | 106 #define C_VBUCTRL 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB |
107 #define C_VBDCTRL 0x098c | TRUE // PGA_DL 0dB, Volume 0dB | 107 #define C_VBDCTRL 0x098c | TRUE // PGA_DL 0dB, Volume 0dB |
190 }T_RF_AGC_BAND; | 190 }T_RF_AGC_BAND; |
191 | 191 |
192 /************************************/ | 192 /************************************/ |
193 /* Ramp definitions */ | 193 /* Ramp definitions */ |
194 /************************************/ | 194 /************************************/ |
195 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) | 195 #if ((ANALOG == 1) || (ANALOG == 2)) |
196 typedef struct | 196 typedef struct |
197 { | 197 { |
198 UWORD8 ramp_up [16]; // Ramp-up profile | 198 UWORD8 ramp_up [16]; // Ramp-up profile |
199 UWORD8 ramp_down [16]; // Ramp-down profile | 199 UWORD8 ramp_down [16]; // Ramp-down profile |
200 } | 200 } |
438 #define ABB_TABLE_SIZE 16 | 438 #define ABB_TABLE_SIZE 16 |
439 | 439 |
440 // Note that this translation is probably not needed at all. But until L1 is | 440 // Note that this translation is probably not needed at all. But until L1 is |
441 // (maybe) changed to simply initialize the ABB from a table of words, we | 441 // (maybe) changed to simply initialize the ABB from a table of words, we |
442 // use this to make things more easy-readable. | 442 // use this to make things more easy-readable. |
443 #if (ANLG_FAM == 1) | 443 #if (ANALOG == 1) |
444 enum ABB_REGISTERS { | 444 enum ABB_REGISTERS { |
445 ABB_AFCCTLADD = 0, | 445 ABB_AFCCTLADD = 0, |
446 ABB_VBUCTRL, | 446 ABB_VBUCTRL, |
447 ABB_VBDCTRL, | 447 ABB_VBDCTRL, |
448 ABB_BBCTRL, | 448 ABB_BBCTRL, |
452 ABB_DAI_ON_OFF, | 452 ABB_DAI_ON_OFF, |
453 ABB_AUXDAC, | 453 ABB_AUXDAC, |
454 ABB_VBCTRL, | 454 ABB_VBCTRL, |
455 ABB_APCDEL1 | 455 ABB_APCDEL1 |
456 }; | 456 }; |
457 #elif (ANLG_FAM == 2) | 457 #elif (ANALOG == 2) |
458 enum ABB_REGISTERS { | 458 enum ABB_REGISTERS { |
459 ABB_AFCCTLADD = 0, | 459 ABB_AFCCTLADD = 0, |
460 ABB_VBUCTRL, | 460 ABB_VBUCTRL, |
461 ABB_VBDCTRL, | 461 ABB_VBDCTRL, |
462 ABB_BBCTRL, | 462 ABB_BBCTRL, |