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comparison gsm-fw/L1/cust0/l1_rf8.h @ 152:26472940e5b0

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l1_rf<N>.h headers preened
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 04:59:55 +0000
parents d0de2d0a426d
children
comparison
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151:d0de2d0a426d 152:26472940e5b0
29 /******************************************************/ 29 /******************************************************/
30 /* TXPWR configuration... */ 30 /* TXPWR configuration... */
31 /* Fixed TXPWR value when GSM management is disabled. */ 31 /* Fixed TXPWR value when GSM management is disabled. */
32 /******************************************************/ 32 /******************************************************/
33 33
34 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 34 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
35 // #define FIXED_TXPWR ((0xFC << 6) | AUXAPC | FALSE) // TXPWR=10, value=252 35 // #define FIXED_TXPWR ((0xFC << 6) | AUXAPC | FALSE) // TXPWR=10, value=252
36 // #define FIXED_TXPWR ((0x28 << 6) | AUXAPC | FALSE) 36 // #define FIXED_TXPWR ((0x28 << 6) | AUXAPC | FALSE)
37 #define FIXED_TXPWR ((0x68 << 6) | AUXAPC | FALSE) // TXPWR=15 37 #define FIXED_TXPWR ((0x68 << 6) | AUXAPC | FALSE) // TXPWR=15
38 #endif 38 #endif
39 39
44 44
45 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal 45 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
46 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block 46 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
47 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block 47 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
48 48
49 #if (ANLG_FAM == 1) 49 #if (ANALOG == 1)
50 #define UL_ABB_DELAY 0 // modulator input to output delay, theoretical value is 6, needs to be checked 50 #define UL_ABB_DELAY 0 // modulator input to output delay, theoretical value is 6, needs to be checked
51 #endif 51 #endif
52 52
53 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 53 #if ((ANALOG == 2) || (ANALOG == 3))
54 #define UL_ABB_DELAY 3 // modulator input to output delay 54 #define UL_ABB_DELAY 3 // modulator input to output delay
55 #endif 55 #endif
56 56
57 /************************************/ 57 /************************************/
58 /* TX Propagation delay... */ 58 /* TX Propagation delay... */
59 /************************************/ 59 /************************************/
60 60
61 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 61 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
62 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 62 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
63 #endif 63 #endif
64 64
65 /************************************/ 65 /************************************/
66 /* Initial value for APC DELAY */ 66 /* Initial value for APC DELAY */
67 /************************************/ 67 /************************************/
68 68
69 #if (ANLG_FAM == 1) 69 #if (ANALOG == 1)
70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
71 #define APCDEL_DOWN 2 // minimum value: 2 71 #define APCDEL_DOWN 2 // minimum value: 2
72 #define APCDEL_UP (6+5) // minimum value: 6 72 #define APCDEL_UP (6+5) // minimum value: 6
73 #endif 73 #endif
74 74
75 #if (ANLG_FAM == 2) || (ANLG_FAM == 3) 75 #if (ANALOG == 2) || (ANALOG == 3)
76 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 76 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
77 #define APCDEL_DOWN (2+0) // minimum value: 2 77 #define APCDEL_DOWN (2+0) // minimum value: 2
78 #define APCDEL_UP (6+2) // minimum value: 6 78 #define APCDEL_UP (6+2) // minimum value: 6
79 #endif 79 #endif
80 80
92 92
93 /************************************/ 93 /************************************/
94 /* Baseband registers */ 94 /* Baseband registers */
95 /************************************/ 95 /************************************/
96 96
97 #if (ANLG_FAM == 1) 97 #if (ANALOG == 1)
98 // Omega registers values will be programmed at 1st DSP communication interrupt 98 // Omega registers values will be programmed at 1st DSP communication interrupt
99 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 99 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
100 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 100 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
101 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB 101 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
102 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB 102 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
110 // BULRUDEL will be initialized on rach only .... 110 // BULRUDEL will be initialized on rach only ....
111 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) 111 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
112 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' 112 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
113 #endif 113 #endif
114 114
115 #if (ANLG_FAM == 2) 115 #if (ANALOG == 2)
116 // IOTA registers values will be programmed at 1st DSP communication interrupt 116 // IOTA registers values will be programmed at 1st DSP communication interrupt
117 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG 117 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
118 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 118 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
119 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB 119 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
120 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB 120 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
133 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V 133 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
134 // Monoslot, Vpp=8/15*Vref 134 // Monoslot, Vpp=8/15*Vref
135 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB 135 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
136 #endif 136 #endif
137 137
138 #if (ANLG_FAM == 3) 138 #if (ANALOG == 3)
139 // SYREN registers values will be programmed at 1st DSP communication interrupt 139 // SYREN registers values will be programmed at 1st DSP communication interrupt
140 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG 140 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
141 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 141 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
142 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3dB 142 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3dB
143 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB 143 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
245 245
246 /************************************/ 246 /************************************/
247 /* Ramp definitions */ 247 /* Ramp definitions */
248 /************************************/ 248 /************************************/
249 249
250 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 250 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
251 typedef struct 251 typedef struct
252 { 252 {
253 UWORD8 ramp_up [16]; // Ramp-up profile 253 UWORD8 ramp_up [16]; // Ramp-up profile
254 UWORD8 ramp_down [16]; // Ramp-down profile 254 UWORD8 ramp_down [16]; // Ramp-down profile
255 } 255 }
496 496
497 /************************************/ 497 /************************************/
498 /* ABB (Omega) Initialization */ 498 /* ABB (Omega) Initialization */
499 /************************************/ 499 /************************************/
500 500
501 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) 501 #if ((ANALOG == 1) || (ANALOG == 2))
502 #define ABB_TABLE_SIZE 16 502 #define ABB_TABLE_SIZE 16
503 #endif 503 #endif
504 504
505 #if (ANLG_FAM == 3) 505 #if (ANALOG == 3)
506 #define ABB_TABLE_SIZE 22 506 #define ABB_TABLE_SIZE 22
507 #endif 507 #endif
508 508
509 // Note that this translation is probably not needed at all. But until L1 is 509 // Note that this translation is probably not needed at all. But until L1 is
510 // (maybe) changed to simply initialize the ABB from a table of words, we 510 // (maybe) changed to simply initialize the ABB from a table of words, we
511 // use this to make things more easy-readable. 511 // use this to make things more easy-readable.
512 512
513 #if (ANLG_FAM == 1) 513 #if (ANALOG == 1)
514 enum ABB_REGISTERS { 514 enum ABB_REGISTERS {
515 ABB_AFCCTLADD = 0, 515 ABB_AFCCTLADD = 0,
516 ABB_VBUCTRL, 516 ABB_VBUCTRL,
517 ABB_VBDCTRL, 517 ABB_VBDCTRL,
518 ABB_BBCTRL, 518 ABB_BBCTRL,
524 ABB_VBCTRL, 524 ABB_VBCTRL,
525 ABB_APCDEL1 525 ABB_APCDEL1
526 }; 526 };
527 #endif 527 #endif
528 528
529 #if (ANLG_FAM == 2) 529 #if (ANALOG == 2)
530 enum ABB_REGISTERS { 530 enum ABB_REGISTERS {
531 ABB_AFCCTLADD = 0, 531 ABB_AFCCTLADD = 0,
532 ABB_VBUCTRL, 532 ABB_VBUCTRL,
533 ABB_VBDCTRL, 533 ABB_VBDCTRL,
534 ABB_BBCTRL, 534 ABB_BBCTRL,
543 ABB_APCDEL1, 543 ABB_APCDEL1,
544 ABB_APCDEL2 544 ABB_APCDEL2
545 }; 545 };
546 #endif 546 #endif
547 547
548 #if (ANLG_FAM == 3) 548 #if (ANALOG == 3)
549 enum ABB_REGISTERS { 549 enum ABB_REGISTERS {
550 ABB_AFCCTLADD = 0, 550 ABB_AFCCTLADD = 0,
551 ABB_VBUCTRL, 551 ABB_VBUCTRL,
552 ABB_VBDCTRL, 552 ABB_VBDCTRL,
553 ABB_BBCTRL, 553 ABB_BBCTRL,