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comparison gsm-fw/L1/cfile/l1_init.c @ 548:67ab5f240b7d

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gsm-fw/L1/cfile/*.c: s/ANLG_FAM/ANALOG/
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 03 Aug 2014 16:13:52 +0000
parents 96a96ec34139
children a418c48046ad
comparison
equal deleted inserted replaced
547:32f7494783db 548:67ab5f240b7d
97 #endif 97 #endif
98 98
99 99
100 #include "spi_drv.h" 100 #include "spi_drv.h"
101 #include "abb.h" 101 #include "abb.h"
102 #if (ANLG_FAM != 11) 102 #if (ANALOG != 11)
103 #include "abb_core_inth.h" 103 #include "abb_core_inth.h"
104 #endif 104 #endif
105 105
106 #if TESTMODE 106 #if TESTMODE
107 #include "l1tm_defty.h" 107 #include "l1tm_defty.h"
194 #endif 194 #endif
195 195
196 #include <string.h> 196 #include <string.h>
197 #include <stdio.h> 197 #include <stdio.h>
198 198
199 #if (ANLG_FAM == 11) 199 #if (ANALOG == 11)
200 #include "bspTwl3029_I2c.h" 200 #include "bspTwl3029_I2c.h"
201 #include "bspTwl3029_Aud_Map.h" 201 #include "bspTwl3029_Aud_Map.h"
202 #include "bspTwl3029_Madc.h" 202 #include "bspTwl3029_Madc.h"
203 #endif 203 #endif
204 //OMAPS148175 204 //OMAPS148175
205 #include "l1_drp_if.h" 205 #include "l1_drp_if.h"
206 #include "drp_main.h" 206 #include "drp_main.h"
207 // 207 //
208 #if (ANLG_FAM == 11) 208 #if (ANALOG == 11)
209 #if (L1_MADC_ON == 1) 209 #if (L1_MADC_ON == 1)
210 extern BspTwl3029_MadcResults l1_madc_results; 210 extern BspTwl3029_MadcResults l1_madc_results;
211 extern void l1a_madc_callback(void); 211 extern void l1a_madc_callback(void);
212 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC 212 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
213 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC 213 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff 377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff
378 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0 378 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff 379 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff
380 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0; 380 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0;
381 381
382 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11)) 382 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
383 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11) 383 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11)
384 #endif 384 #endif
385 385
386 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 386 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
387 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits 387 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits
388 #endif 388 #endif
389 #if (ANLG_FAM == 11) 389 #if (ANALOG == 11)
390 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits 390 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits
391 #endif 391 #endif
392 392
393 #if (DSP == 32) 393 #if (DSP == 32)
394 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2; 394 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2;
758 1 /* arbitrary value for arfcn*/); 758 1 /* arbitrary value for arfcn*/);
759 } 759 }
760 #endif 760 #endif
761 761
762 762
763 #if (ANLG_FAM == 1) 763 #if (ANALOG == 1)
764 // Omega registers values will be programmed at 1st DSP communication interrupt 764 // Omega registers values will be programmed at 1st DSP communication interrupt
765 765
766 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG 766 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
767 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset 767 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
768 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute 768 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
784 dsp_ndb_ptr->d_bulgcal = 0x0000; 784 dsp_ndb_ptr->d_bulgcal = 0x0000;
785 dsp_ndb_ptr->d_vbctrl2 = 0x0000; 785 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
786 dsp_ndb_ptr->d_apcdel2 = 0x0000; 786 dsp_ndb_ptr->d_apcdel2 = 0x0000;
787 #endif 787 #endif
788 #endif 788 #endif
789 #if (ANLG_FAM == 2) 789 #if (ANALOG == 2)
790 // Iota registers values will be programmed at 1st DSP communication interrupt 790 // Iota registers values will be programmed at 1st DSP communication interrupt
791 791
792 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG 792 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
793 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset 793 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
794 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute 794 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
805 805
806 // APCDEL1 will be initialized on rach only .... 806 // APCDEL1 will be initialized on rach only ....
807 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; 807 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
808 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; 808 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
809 #endif 809 #endif
810 #if (ANLG_FAM == 3) 810 #if (ANALOG == 3)
811 // Syren registers values will be programmed at 1st DSP communication interrupt 811 // Syren registers values will be programmed at 1st DSP communication interrupt
812 812
813 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG 813 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
814 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset 814 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
815 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute 815 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
840 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero 840 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero
841 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense) 841 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense)
842 842
843 #endif 843 #endif
844 844
845 #if (ANLG_FAM == 11) 845 #if (ANALOG == 11)
846 // The following settings need to be done only in L1 StandALoen as PSP would 846 // The following settings need to be done only in L1 StandALoen as PSP would
847 // do in the case of full PS Build... 847 // do in the case of full PS Build...
848 848
849 //Set the CTRL3 register 849 //Set the CTRL3 register
850 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, 850 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,