diff nuc-fw/bsp/clkm.h @ 115:1e41550feec5

nuc-fw: Init_Target() reconstructed
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 27 Oct 2013 04:43:04 +0000
parents 91460c8957f0
children
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--- a/nuc-fw/bsp/clkm.h	Thu Oct 24 02:47:14 2013 +0000
+++ b/nuc-fw/bsp/clkm.h	Sun Oct 27 04:43:04 2013 +0000
@@ -107,19 +107,19 @@
   #define DPLL_PLL_DIV      0x0060     // Mask of division factor configuration
   #define DPLL_PLL_MULT     0x0F80     // Mask of multiply factor configuration
 
-  #define DPLL_BYPASS_DIV_1 0x00       // Configuration of bypass mode divided by 1
-  #define DPLL_BYPASS_DIV_2 0x01       // Configuration of bypass mode divided by 2
-  #define DPLL_BYPASS_DIV_4 0x10       // Configuration of bypass mode divided by 4
-  
+  #define DPLL_BYPASS_DIV_1 0x0        // Configuration of bypass mode divided by 1
+  #define DPLL_BYPASS_DIV_2 0x1        // Configuration of bypass mode divided by 2
+  #define DPLL_BYPASS_DIV_4 0x2        // Configuration of bypass mode divided by 4
+
   #define DPLL_BYPASS_DIV_OFFSET 2     // Offset of bypass bits configuration
   #define DPLL_PLL_DIV_OFFSET    5     // Offset of division bits configuration
   #define DPLL_PLL_MULT_OFFSET   7     // Offset of multiply bits configuration
-  
+
   #define DPLL_LOCK_DIV_1   0x0000     // Divide by 1 when DPLL is locked
   #define DPLL_LOCK_DIV_2   0x0001     // Divide by 2 when DPLL is locked
   #define DPLL_LOCK_DIV_3   0x0002     // Divide by 3 when DPLL is locked
   #define DPLL_LOCK_DIV_4   0x0003     // Divide by 4 when DPLL is locked
-  
+
 #else
   #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6)     /* Lead PLL */
   #define CLKM_PLONOFF	0x0001         // PLL enable signal
@@ -260,8 +260,12 @@
 /*
  * NOTE: the version of the CLKM_INITCNTL() macro in the Sotomodem source
  * does |= instead of =.  It remains to be investigated which is more correct.
+ *
+ * For now I'll define the ORing version under a different (and more
+ * descriptive) name: CLKM_CNTL_OR.
  */
 
+#define CLKM_CNTL_OR(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
 
 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
   /*---------------------------------------------------------------/